13313e0e2SMark Jonas/* 23313e0e2SMark Jonas * (C) Copyright 2008 33313e0e2SMark Jonas * Mark Jonas <mark.jonas@de.bosch.com> 43313e0e2SMark Jonas * 53313e0e2SMark Jonas * (C) Copyright 2007 63313e0e2SMark Jonas * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> 73313e0e2SMark Jonas * 83313e0e2SMark Jonas * board/mpr2/lowlevel_init.S 93313e0e2SMark Jonas * 10*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 113313e0e2SMark Jonas */ 12f7e78f3bSJean-Christophe PLAGNIOL-VILLARD#include <asm/macro.h> 133313e0e2SMark Jonas 143313e0e2SMark Jonas .global lowlevel_init 153313e0e2SMark Jonas 163313e0e2SMark Jonas .text 173313e0e2SMark Jonas .align 2 183313e0e2SMark Jonas 193313e0e2SMark Jonaslowlevel_init: 203313e0e2SMark Jonas 213313e0e2SMark Jonas/* 223313e0e2SMark Jonas * Set frequency multipliers and dividers in FRQCR. 233313e0e2SMark Jonas */ 24f7e78f3bSJean-Christophe PLAGNIOL-VILLARD write16 WTCSR_A, WTCSR_D 253313e0e2SMark Jonas 26f7e78f3bSJean-Christophe PLAGNIOL-VILLARD write16 WTCNT_A, WTCNT_D 273313e0e2SMark Jonas 28f7e78f3bSJean-Christophe PLAGNIOL-VILLARD write16 FRQCR_A, FRQCR_D 293313e0e2SMark Jonas 303313e0e2SMark Jonas/* 313313e0e2SMark Jonas * Setup CS0 (Flash). 323313e0e2SMark Jonas */ 33f7e78f3bSJean-Christophe PLAGNIOL-VILLARD write32 CS0BCR_A, CS0BCR_D 343313e0e2SMark Jonas 35f7e78f3bSJean-Christophe PLAGNIOL-VILLARD write32 CS0WCR_A, CS0WCR_D 363313e0e2SMark Jonas 373313e0e2SMark Jonas/* 383313e0e2SMark Jonas * Setup CS3 (SDRAM). 393313e0e2SMark Jonas */ 40f7e78f3bSJean-Christophe PLAGNIOL-VILLARD write32 CS3BCR_A, CS3BCR_D 413313e0e2SMark Jonas 42f7e78f3bSJean-Christophe PLAGNIOL-VILLARD write32 CS3WCR_A, CS3WCR_D 433313e0e2SMark Jonas 44f7e78f3bSJean-Christophe PLAGNIOL-VILLARD write32 SDCR_A, SDCR_D1 453313e0e2SMark Jonas 46f7e78f3bSJean-Christophe PLAGNIOL-VILLARD write32 RTCSR_A, RTCSR_D 473313e0e2SMark Jonas 48f7e78f3bSJean-Christophe PLAGNIOL-VILLARD write32 RTCNT_A, RTCNT_D 493313e0e2SMark Jonas 50f7e78f3bSJean-Christophe PLAGNIOL-VILLARD write32 RTCOR_A, RTCOR_D 513313e0e2SMark Jonas 52f7e78f3bSJean-Christophe PLAGNIOL-VILLARD write32 SDCR_A, SDCR_D2 533313e0e2SMark Jonas 543313e0e2SMark Jonas mov.l SDMR3_A, r1 553313e0e2SMark Jonas mov.l SDMR3_D, r0 563313e0e2SMark Jonas add r0, r1 573313e0e2SMark Jonas mov #0, r0 583313e0e2SMark Jonas mov.w r0, @r1 593313e0e2SMark Jonas 603313e0e2SMark Jonas rts 613313e0e2SMark Jonas nop 623313e0e2SMark Jonas 633313e0e2SMark Jonas .align 4 643313e0e2SMark Jonas 653313e0e2SMark Jonas/* 663313e0e2SMark Jonas * Configuration for MPR2 A.3 through A.7 673313e0e2SMark Jonas */ 683313e0e2SMark Jonas 693313e0e2SMark Jonas/* 703313e0e2SMark Jonas * PLL Settings 713313e0e2SMark Jonas */ 723594f198SNobuhiro IwamatsuFRQCR_D: .word 0x1103 /* I:B:P=8:4:2 */ 733594f198SNobuhiro IwamatsuWTCNT_D: .word 0x5A00 /* start counting at zero */ 743594f198SNobuhiro IwamatsuWTCSR_D: .word 0xA507 /* divide by 4096 */ 753594f198SNobuhiro Iwamatsu.align 2 763313e0e2SMark Jonas/* 773313e0e2SMark Jonas * Spansion S29GL256N11 @ 48 MHz 783313e0e2SMark Jonas */ 79e4430779SJean-Christophe PLAGNIOL-VILLARD/* 1 idle cycle inserted, normal space, 16 bit */ 80e4430779SJean-Christophe PLAGNIOL-VILLARDCS0BCR_D: .long 0x12490400 81e4430779SJean-Christophe PLAGNIOL-VILLARD/* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */ 82e4430779SJean-Christophe PLAGNIOL-VILLARDCS0WCR_D: .long 0x00000340 833313e0e2SMark Jonas 843313e0e2SMark Jonas/* 853313e0e2SMark Jonas * Samsung K4S511632B-UL75 @ 48 MHz 863313e0e2SMark Jonas * Micron MT48LC32M16A2-75 @ 48 MHz 873313e0e2SMark Jonas */ 88e4430779SJean-Christophe PLAGNIOL-VILLARD/* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */ 89e4430779SJean-Christophe PLAGNIOL-VILLARDCS3BCR_D: .long 0x10004400 90e4430779SJean-Christophe PLAGNIOL-VILLARD/* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */ 91e4430779SJean-Christophe PLAGNIOL-VILLARDCS3WCR_D: .long 0x00000091 92e4430779SJean-Christophe PLAGNIOL-VILLARD/* no refresh, 13 rows, 10 cols, NO bank active mode */ 93e4430779SJean-Christophe PLAGNIOL-VILLARDSDCR_D1: .long 0x00000012 943313e0e2SMark JonasSDCR_D2: .long 0x00000812 /* refresh */ 953313e0e2SMark JonasRTCSR_D: .long 0xA55A0008 /* 1/4, once */ 963313e0e2SMark JonasRTCNT_D: .long 0xA55A005D /* count 93 */ 973313e0e2SMark JonasRTCOR_D: .long 0xa55a005d /* count 93 */ 98e4430779SJean-Christophe PLAGNIOL-VILLARD/* mode register CL2, burst read and SINGLE WRITE */ 99e4430779SJean-Christophe PLAGNIOL-VILLARDSDMR3_D: .long 0x440 1003313e0e2SMark Jonas 1013313e0e2SMark Jonas/* 1023313e0e2SMark Jonas * Registers 1033313e0e2SMark Jonas */ 1043313e0e2SMark Jonas 1053313e0e2SMark JonasFRQCR_A: .long 0xA415FF80 1063313e0e2SMark JonasWTCNT_A: .long 0xA415FF84 1073313e0e2SMark JonasWTCSR_A: .long 0xA415FF86 1083313e0e2SMark Jonas 1093313e0e2SMark Jonas#define BSC_BASE 0xA4FD0000 1103313e0e2SMark JonasCS0BCR_A: .long BSC_BASE + 0x04 1113313e0e2SMark JonasCS3BCR_A: .long BSC_BASE + 0x0C 1123313e0e2SMark JonasCS0WCR_A: .long BSC_BASE + 0x24 1133313e0e2SMark JonasCS3WCR_A: .long BSC_BASE + 0x2C 1143313e0e2SMark JonasSDCR_A: .long BSC_BASE + 0x44 1153313e0e2SMark JonasRTCSR_A: .long BSC_BASE + 0x48 1163313e0e2SMark JonasRTCNT_A: .long BSC_BASE + 0x4C 1173313e0e2SMark JonasRTCOR_A: .long BSC_BASE + 0x50 1183313e0e2SMark JonasSDMR3_A: .long BSC_BASE + 0x5000 119