1bc8f8c26SIlya Yanok /* 2bc8f8c26SIlya Yanok * Copyright (C) 2007 Freescale Semiconductor, Inc. 3bc8f8c26SIlya Yanok * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com 4bc8f8c26SIlya Yanok * 5bc8f8c26SIlya Yanok * This files is mostly identical to the original from 6bc8f8c26SIlya Yanok * board/freescale/mpc8308rdb/sdram.c 7bc8f8c26SIlya Yanok * 81a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 9bc8f8c26SIlya Yanok */ 10bc8f8c26SIlya Yanok 11bc8f8c26SIlya Yanok #include <common.h> 12bc8f8c26SIlya Yanok #include <mpc83xx.h> 13bc8f8c26SIlya Yanok 14bc8f8c26SIlya Yanok #include <asm/bitops.h> 15bc8f8c26SIlya Yanok #include <asm/io.h> 16bc8f8c26SIlya Yanok 17bc8f8c26SIlya Yanok #include <asm/processor.h> 18bc8f8c26SIlya Yanok 19bc8f8c26SIlya Yanok DECLARE_GLOBAL_DATA_PTR; 20bc8f8c26SIlya Yanok 21bc8f8c26SIlya Yanok /* Fixed sdram init -- doesn't use serial presence detect. 22bc8f8c26SIlya Yanok * 23bc8f8c26SIlya Yanok * This is useful for faster booting in configs where the RAM is unlikely 24bc8f8c26SIlya Yanok * to be changed, or for things like NAND booting where space is tight. 25bc8f8c26SIlya Yanok */ 26bc8f8c26SIlya Yanok static long fixed_sdram(void) 27bc8f8c26SIlya Yanok { 28bc8f8c26SIlya Yanok immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 29bc8f8c26SIlya Yanok u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; 30bc8f8c26SIlya Yanok u32 msize_log2 = __ilog2(msize); 31bc8f8c26SIlya Yanok 32bc8f8c26SIlya Yanok out_be32(&im->sysconf.ddrlaw[0].bar, 33bc8f8c26SIlya Yanok CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000); 34bc8f8c26SIlya Yanok out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); 35bc8f8c26SIlya Yanok out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); 36bc8f8c26SIlya Yanok 37bc8f8c26SIlya Yanok out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); 38bc8f8c26SIlya Yanok out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); 39bc8f8c26SIlya Yanok 40bc8f8c26SIlya Yanok /* Currently we use only one CS, so disable the other bank. */ 41bc8f8c26SIlya Yanok out_be32(&im->ddr.cs_config[1], 0); 42bc8f8c26SIlya Yanok 43bc8f8c26SIlya Yanok out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); 44bc8f8c26SIlya Yanok out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); 45bc8f8c26SIlya Yanok out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); 46bc8f8c26SIlya Yanok out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); 47bc8f8c26SIlya Yanok out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); 48bc8f8c26SIlya Yanok 49bc8f8c26SIlya Yanok out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); 50bc8f8c26SIlya Yanok out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); 51bc8f8c26SIlya Yanok out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); 52bc8f8c26SIlya Yanok out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); 53bc8f8c26SIlya Yanok 54bc8f8c26SIlya Yanok out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); 55bc8f8c26SIlya Yanok sync(); 56bc8f8c26SIlya Yanok 57bc8f8c26SIlya Yanok /* enable DDR controller */ 58bc8f8c26SIlya Yanok setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); 59bc8f8c26SIlya Yanok sync(); 60bc8f8c26SIlya Yanok 61bc8f8c26SIlya Yanok return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize); 62bc8f8c26SIlya Yanok } 63bc8f8c26SIlya Yanok 64*088454cdSSimon Glass int initdram(void) 65bc8f8c26SIlya Yanok { 66bc8f8c26SIlya Yanok immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 67bc8f8c26SIlya Yanok u32 msize; 68bc8f8c26SIlya Yanok 69bc8f8c26SIlya Yanok if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im) 70bc8f8c26SIlya Yanok return -1; 71bc8f8c26SIlya Yanok 72bc8f8c26SIlya Yanok /* DDR SDRAM */ 73bc8f8c26SIlya Yanok msize = fixed_sdram(); 74bc8f8c26SIlya Yanok 75*088454cdSSimon Glass /* set total bus SDRAM size(bytes) -- DDR */ 76*088454cdSSimon Glass gd->ram_size = msize; 77*088454cdSSimon Glass 78*088454cdSSimon Glass return 0; 79bc8f8c26SIlya Yanok } 80