1*2a61eff6SStefan Roese /* 2*2a61eff6SStefan Roese * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering 3*2a61eff6SStefan Roese * 4*2a61eff6SStefan Roese * Copyright (C) 2006 Micronas GmbH 5*2a61eff6SStefan Roese * 6*2a61eff6SStefan Roese * This program is free software; you can redistribute it and/or 7*2a61eff6SStefan Roese * modify it under the terms of the GNU General Public License as 8*2a61eff6SStefan Roese * published by the Free Software Foundation; either version 2 of 9*2a61eff6SStefan Roese * the License, or (at your option) any later version. 10*2a61eff6SStefan Roese * 11*2a61eff6SStefan Roese * This program is distributed in the hope that it will be useful, 12*2a61eff6SStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 13*2a61eff6SStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14*2a61eff6SStefan Roese * GNU General Public License for more details. 15*2a61eff6SStefan Roese * 16*2a61eff6SStefan Roese * You should have received a copy of the GNU General Public License 17*2a61eff6SStefan Roese * along with this program; if not, write to the Free Software 18*2a61eff6SStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19*2a61eff6SStefan Roese * MA 02111-1307 USA 20*2a61eff6SStefan Roese */ 21*2a61eff6SStefan Roese 22*2a61eff6SStefan Roese /* 23*2a61eff6SStefan Roese * Premium & Platinum register addresses/definitions seem to be 24*2a61eff6SStefan Roese * identical, so we only need to use one file for both platforms. 25*2a61eff6SStefan Roese */ 26*2a61eff6SStefan Roese 27*2a61eff6SStefan Roese #ifndef _REG_FWSRAM_H_ 28*2a61eff6SStefan Roese #define _REG_FWSRAM_H_ 29*2a61eff6SStefan Roese 30*2a61eff6SStefan Roese #define FWSRAM_BASE 0x00030000 31*2a61eff6SStefan Roese 32*2a61eff6SStefan Roese /* Relative offsets of the register adresses */ 33*2a61eff6SStefan Roese 34*2a61eff6SStefan Roese #define FWSRAM_SR_ADDR_OFFSET_OFFS 0x00002000 35*2a61eff6SStefan Roese #define FWSRAM_SR_ADDR_OFFSET(base) ((base) + FWSRAM_SR_ADDR_OFFSET_OFFS) 36*2a61eff6SStefan Roese #define FWSRAM_TOP_BOOT_LOG_OFFS 0x00002004 37*2a61eff6SStefan Roese #define FWSRAM_TOP_BOOT_LOG(base) ((base) + FWSRAM_TOP_BOOT_LOG_OFFS) 38*2a61eff6SStefan Roese #define FWSRAM_TOP_ROM_KBIST_OFFS 0x00002008 39*2a61eff6SStefan Roese #define FWSRAM_TOP_ROM_KBIST(base) ((base) + FWSRAM_TOP_ROM_KBIST_OFFS) 40*2a61eff6SStefan Roese #define FWSRAM_TOP_CID1_H_OFFS 0x0000200C 41*2a61eff6SStefan Roese #define FWSRAM_TOP_CID1_H(base) ((base) + FWSRAM_TOP_CID1_H_OFFS) 42*2a61eff6SStefan Roese #define FWSRAM_TOP_CID1_L_OFFS 0x00002010 43*2a61eff6SStefan Roese #define FWSRAM_TOP_CID1_L(base) ((base) + FWSRAM_TOP_CID1_L_OFFS) 44*2a61eff6SStefan Roese #define FWSRAM_TOP_CID2_H_OFFS 0x00002014 45*2a61eff6SStefan Roese #define FWSRAM_TOP_CID2_H(base) ((base) + FWSRAM_TOP_CID2_H_OFFS) 46*2a61eff6SStefan Roese #define FWSRAM_TOP_CID2_L_OFFS 0x00002018 47*2a61eff6SStefan Roese #define FWSRAM_TOP_CID2_L(base) ((base) + FWSRAM_TOP_CID2_L_OFFS) 48*2a61eff6SStefan Roese #define FWSRAM_TOP_TDO_CFG_OFFS 0x0000203C 49*2a61eff6SStefan Roese #define FWSRAM_TOP_TDO_CFG(base) ((base) + FWSRAM_TOP_TDO_CFG_OFFS) 50*2a61eff6SStefan Roese #define FWSRAM_TOP_GPIO2_0_CFG_OFFS 0x00002040 51*2a61eff6SStefan Roese #define FWSRAM_TOP_GPIO2_0_CFG(base) ((base) + FWSRAM_TOP_GPIO2_0_CFG_OFFS) 52*2a61eff6SStefan Roese #define FWSRAM_TOP_GPIO2_1_CFG_OFFS 0x00002044 53*2a61eff6SStefan Roese #define FWSRAM_TOP_GPIO2_1_CFG(base) ((base) + FWSRAM_TOP_GPIO2_1_CFG_OFFS) 54*2a61eff6SStefan Roese #define FWSRAM_TOP_GPIO2_2_CFG_OFFS 0x00002048 55*2a61eff6SStefan Roese #define FWSRAM_TOP_GPIO2_2_CFG(base) ((base) + FWSRAM_TOP_GPIO2_2_CFG_OFFS) 56*2a61eff6SStefan Roese #define FWSRAM_TOP_GPIO2_3_CFG_OFFS 0x0000204C 57*2a61eff6SStefan Roese #define FWSRAM_TOP_GPIO2_3_CFG(base) ((base) + FWSRAM_TOP_GPIO2_3_CFG_OFFS) 58*2a61eff6SStefan Roese #define FWSRAM_TOP_GPIO2_4_CFG_OFFS 0x00002050 59*2a61eff6SStefan Roese #define FWSRAM_TOP_GPIO2_4_CFG(base) ((base) + FWSRAM_TOP_GPIO2_4_CFG_OFFS) 60*2a61eff6SStefan Roese #define FWSRAM_TOP_GPIO2_5_CFG_OFFS 0x00002054 61*2a61eff6SStefan Roese #define FWSRAM_TOP_GPIO2_5_CFG(base) ((base) + FWSRAM_TOP_GPIO2_5_CFG_OFFS) 62*2a61eff6SStefan Roese #define FWSRAM_TOP_GPIO2_6_CFG_OFFS 0x00002058 63*2a61eff6SStefan Roese #define FWSRAM_TOP_GPIO2_6_CFG(base) ((base) + FWSRAM_TOP_GPIO2_6_CFG_OFFS) 64*2a61eff6SStefan Roese #define FWSRAM_TOP_GPIO2_7_CFG_OFFS 0x0000205C 65*2a61eff6SStefan Roese #define FWSRAM_TOP_GPIO2_7_CFG(base) ((base) + FWSRAM_TOP_GPIO2_7_CFG_OFFS) 66*2a61eff6SStefan Roese #define FWSRAM_TOP_SCL_CFG_OFFS 0x00002060 67*2a61eff6SStefan Roese #define FWSRAM_TOP_SCL_CFG(base) ((base) + FWSRAM_TOP_SCL_CFG_OFFS) 68*2a61eff6SStefan Roese #define FWSRAM_TOP_SDA_CFG_OFFS 0x00002064 69*2a61eff6SStefan Roese #define FWSRAM_TOP_SDA_CFG(base) ((base) + FWSRAM_TOP_SDA_CFG_OFFS) 70*2a61eff6SStefan Roese #define FWSRAM_NO_MCM_FLASH_OFFS 0x00002068 71*2a61eff6SStefan Roese #define FWSRAM_NO_MCM_FLASH(base) ((base) + FWSRAM_NO_MCM_FLASH_OFFS) 72*2a61eff6SStefan Roese 73*2a61eff6SStefan Roese #endif 74