1*2a61eff6SStefan Roese /* 2*2a61eff6SStefan Roese * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering 3*2a61eff6SStefan Roese * 4*2a61eff6SStefan Roese * Copyright (C) 2006 Micronas GmbH 5*2a61eff6SStefan Roese * 6*2a61eff6SStefan Roese * This program is free software; you can redistribute it and/or 7*2a61eff6SStefan Roese * modify it under the terms of the GNU General Public License as 8*2a61eff6SStefan Roese * published by the Free Software Foundation; either version 2 of 9*2a61eff6SStefan Roese * the License, or (at your option) any later version. 10*2a61eff6SStefan Roese * 11*2a61eff6SStefan Roese * This program is distributed in the hope that it will be useful, 12*2a61eff6SStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 13*2a61eff6SStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14*2a61eff6SStefan Roese * GNU General Public License for more details. 15*2a61eff6SStefan Roese * 16*2a61eff6SStefan Roese * You should have received a copy of the GNU General Public License 17*2a61eff6SStefan Roese * along with this program; if not, write to the Free Software 18*2a61eff6SStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19*2a61eff6SStefan Roese * MA 02111-1307 USA 20*2a61eff6SStefan Roese */ 21*2a61eff6SStefan Roese 22*2a61eff6SStefan Roese #ifndef _REG_EBI_PREMIUM_H_ 23*2a61eff6SStefan Roese #define _REG_EBI_PREMIUM_H_ 24*2a61eff6SStefan Roese 25*2a61eff6SStefan Roese #define EBI_BASE 0x00000000 26*2a61eff6SStefan Roese 27*2a61eff6SStefan Roese /* Relative offsets of the register adresses */ 28*2a61eff6SStefan Roese 29*2a61eff6SStefan Roese #define EBI_CPU_IO_ACCS_OFFS 0x00000000 30*2a61eff6SStefan Roese #define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) 31*2a61eff6SStefan Roese #define EBI_IO_ACCS_DATA_OFFS 0x00000004 32*2a61eff6SStefan Roese #define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS) 33*2a61eff6SStefan Roese #define EBI_CTRL_OFFS 0x00000008 34*2a61eff6SStefan Roese #define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) 35*2a61eff6SStefan Roese #define EBI_IRQ_MASK_OFFS 0x00000010 36*2a61eff6SStefan Roese #define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) 37*2a61eff6SStefan Roese #define EBI_TAG1_SYS_ID_OFFS 0x00000030 38*2a61eff6SStefan Roese #define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS) 39*2a61eff6SStefan Roese #define EBI_TAG2_SYS_ID_OFFS 0x00000040 40*2a61eff6SStefan Roese #define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS) 41*2a61eff6SStefan Roese #define EBI_TAG3_SYS_ID_OFFS 0x00000050 42*2a61eff6SStefan Roese #define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS) 43*2a61eff6SStefan Roese #define EBI_TAG4_SYS_ID_OFFS 0x00000060 44*2a61eff6SStefan Roese #define EBI_TAG4_SYS_ID(base) ((base) + EBI_TAG4_SYS_ID_OFFS) 45*2a61eff6SStefan Roese #define EBI_GEN_DMA_CTRL_OFFS 0x00000070 46*2a61eff6SStefan Roese #define EBI_GEN_DMA_CTRL(base) ((base) + EBI_GEN_DMA_CTRL_OFFS) 47*2a61eff6SStefan Roese #define EBI_STATUS_OFFS 0x00000080 48*2a61eff6SStefan Roese #define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS) 49*2a61eff6SStefan Roese #define EBI_STATUS_DMA_CNT_OFFS 0x00000084 50*2a61eff6SStefan Roese #define EBI_STATUS_DMA_CNT(base) ((base) + EBI_STATUS_DMA_CNT_OFFS) 51*2a61eff6SStefan Roese #define EBI_SIG_LEVEL_OFFS 0x00000088 52*2a61eff6SStefan Roese #define EBI_SIG_LEVEL(base) ((base) + EBI_SIG_LEVEL_OFFS) 53*2a61eff6SStefan Roese #define EBI_CTRL_SIG_ACTLV_OFFS 0x0000008C 54*2a61eff6SStefan Roese #define EBI_CTRL_SIG_ACTLV(base) ((base) + EBI_CTRL_SIG_ACTLV_OFFS) 55*2a61eff6SStefan Roese #define EBI_EXT_ADDR_OFFS 0x000000A0 56*2a61eff6SStefan Roese #define EBI_EXT_ADDR(base) ((base) + EBI_EXT_ADDR_OFFS) 57*2a61eff6SStefan Roese #define EBI_IRQ_STATUS_OFFS 0x000000B0 58*2a61eff6SStefan Roese #define EBI_IRQ_STATUS(base) ((base) + EBI_IRQ_STATUS_OFFS) 59*2a61eff6SStefan Roese #define EBI_DEV1_DMA_EXT_ADDR_OFFS 0x00000100 60*2a61eff6SStefan Roese #define EBI_DEV1_DMA_EXT_ADDR(base) ((base) + EBI_DEV1_DMA_EXT_ADDR_OFFS) 61*2a61eff6SStefan Roese #define EBI_DEV1_EXT_ACC_OFFS 0x00000104 62*2a61eff6SStefan Roese #define EBI_DEV1_EXT_ACC(base) ((base) + EBI_DEV1_EXT_ACC_OFFS) 63*2a61eff6SStefan Roese #define EBI_DEV1_CONFIG1_OFFS 0x00000108 64*2a61eff6SStefan Roese #define EBI_DEV1_CONFIG1(base) ((base) + EBI_DEV1_CONFIG1_OFFS) 65*2a61eff6SStefan Roese #define EBI_DEV1_CONFIG2_OFFS 0x0000010C 66*2a61eff6SStefan Roese #define EBI_DEV1_CONFIG2(base) ((base) + EBI_DEV1_CONFIG2_OFFS) 67*2a61eff6SStefan Roese #define EBI_DEV1_FIFO_CONFIG_OFFS 0x00000110 68*2a61eff6SStefan Roese #define EBI_DEV1_FIFO_CONFIG(base) ((base) + EBI_DEV1_FIFO_CONFIG_OFFS) 69*2a61eff6SStefan Roese #define EBI_DEV1_FLASH_CONF_ST_OFFS 0x00000114 70*2a61eff6SStefan Roese #define EBI_DEV1_FLASH_CONF_ST(base) ((base) + EBI_DEV1_FLASH_CONF_ST_OFFS) 71*2a61eff6SStefan Roese #define EBI_DEV1_DMA_CONFIG1_OFFS 0x00000118 72*2a61eff6SStefan Roese #define EBI_DEV1_DMA_CONFIG1(base) ((base) + EBI_DEV1_DMA_CONFIG1_OFFS) 73*2a61eff6SStefan Roese #define EBI_DEV1_DMA_CONFIG2_OFFS 0x0000011C 74*2a61eff6SStefan Roese #define EBI_DEV1_DMA_CONFIG2(base) ((base) + EBI_DEV1_DMA_CONFIG2_OFFS) 75*2a61eff6SStefan Roese #define EBI_DEV1_TIM1_RD1_OFFS 0x00000124 76*2a61eff6SStefan Roese #define EBI_DEV1_TIM1_RD1(base) ((base) + EBI_DEV1_TIM1_RD1_OFFS) 77*2a61eff6SStefan Roese #define EBI_DEV1_TIM1_RD2_OFFS 0x00000128 78*2a61eff6SStefan Roese #define EBI_DEV1_TIM1_RD2(base) ((base) + EBI_DEV1_TIM1_RD2_OFFS) 79*2a61eff6SStefan Roese #define EBI_DEV1_TIM1_WR1_OFFS 0x0000012C 80*2a61eff6SStefan Roese #define EBI_DEV1_TIM1_WR1(base) ((base) + EBI_DEV1_TIM1_WR1_OFFS) 81*2a61eff6SStefan Roese #define EBI_DEV1_TIM1_WR2_OFFS 0x00000130 82*2a61eff6SStefan Roese #define EBI_DEV1_TIM1_WR2(base) ((base) + EBI_DEV1_TIM1_WR2_OFFS) 83*2a61eff6SStefan Roese #define EBI_DEV1_TIM_EXT_OFFS 0x00000134 84*2a61eff6SStefan Roese #define EBI_DEV1_TIM_EXT(base) ((base) + EBI_DEV1_TIM_EXT_OFFS) 85*2a61eff6SStefan Roese #define EBI_DEV1_TIM2_CFI_RD1_OFFS 0x00000138 86*2a61eff6SStefan Roese #define EBI_DEV1_TIM2_CFI_RD1(base) ((base) + EBI_DEV1_TIM2_CFI_RD1_OFFS) 87*2a61eff6SStefan Roese #define EBI_DEV1_TIM2_CFI_RD2_OFFS 0x0000013C 88*2a61eff6SStefan Roese #define EBI_DEV1_TIM2_CFI_RD2(base) ((base) + EBI_DEV1_TIM2_CFI_RD2_OFFS) 89*2a61eff6SStefan Roese #define EBI_DEV1_TIM3_DMA1_OFFS 0x00000140 90*2a61eff6SStefan Roese #define EBI_DEV1_TIM3_DMA1(base) ((base) + EBI_DEV1_TIM3_DMA1_OFFS) 91*2a61eff6SStefan Roese #define EBI_DEV1_TIM3_DMA2_OFFS 0x00000144 92*2a61eff6SStefan Roese #define EBI_DEV1_TIM3_DMA2(base) ((base) + EBI_DEV1_TIM3_DMA2_OFFS) 93*2a61eff6SStefan Roese #define EBI_DEV1_ACK_RM_CNT_OFFS 0x00000150 94*2a61eff6SStefan Roese #define EBI_DEV1_ACK_RM_CNT(base) ((base) + EBI_DEV1_ACK_RM_CNT_OFFS) 95*2a61eff6SStefan Roese #define EBI_DEV2_DMA_EXT_ADDR_OFFS 0x00000200 96*2a61eff6SStefan Roese #define EBI_DEV2_DMA_EXT_ADDR(base) ((base) + EBI_DEV2_DMA_EXT_ADDR_OFFS) 97*2a61eff6SStefan Roese #define EBI_DEV2_EXT_ACC_OFFS 0x00000204 98*2a61eff6SStefan Roese #define EBI_DEV2_EXT_ACC(base) ((base) + EBI_DEV2_EXT_ACC_OFFS) 99*2a61eff6SStefan Roese #define EBI_DEV2_CONFIG1_OFFS 0x00000208 100*2a61eff6SStefan Roese #define EBI_DEV2_CONFIG1(base) ((base) + EBI_DEV2_CONFIG1_OFFS) 101*2a61eff6SStefan Roese #define EBI_DEV2_CONFIG2_OFFS 0x0000020C 102*2a61eff6SStefan Roese #define EBI_DEV2_CONFIG2(base) ((base) + EBI_DEV2_CONFIG2_OFFS) 103*2a61eff6SStefan Roese #define EBI_DEV2_FIFO_CONFIG_OFFS 0x00000210 104*2a61eff6SStefan Roese #define EBI_DEV2_FIFO_CONFIG(base) ((base) + EBI_DEV2_FIFO_CONFIG_OFFS) 105*2a61eff6SStefan Roese #define EBI_DEV2_FLASH_CONF_ST_OFFS 0x00000214 106*2a61eff6SStefan Roese #define EBI_DEV2_FLASH_CONF_ST(base) ((base) + EBI_DEV2_FLASH_CONF_ST_OFFS) 107*2a61eff6SStefan Roese #define EBI_DEV2_DMA_CONFIG1_OFFS 0x00000218 108*2a61eff6SStefan Roese #define EBI_DEV2_DMA_CONFIG1(base) ((base) + EBI_DEV2_DMA_CONFIG1_OFFS) 109*2a61eff6SStefan Roese #define EBI_DEV2_DMA_CONFIG2_OFFS 0x0000021C 110*2a61eff6SStefan Roese #define EBI_DEV2_DMA_CONFIG2(base) ((base) + EBI_DEV2_DMA_CONFIG2_OFFS) 111*2a61eff6SStefan Roese #define EBI_DEV2_TIM1_RD1_OFFS 0x00000224 112*2a61eff6SStefan Roese #define EBI_DEV2_TIM1_RD1(base) ((base) + EBI_DEV2_TIM1_RD1_OFFS) 113*2a61eff6SStefan Roese #define EBI_DEV2_TIM1_RD2_OFFS 0x00000228 114*2a61eff6SStefan Roese #define EBI_DEV2_TIM1_RD2(base) ((base) + EBI_DEV2_TIM1_RD2_OFFS) 115*2a61eff6SStefan Roese #define EBI_DEV2_TIM1_WR1_OFFS 0x0000022C 116*2a61eff6SStefan Roese #define EBI_DEV2_TIM1_WR1(base) ((base) + EBI_DEV2_TIM1_WR1_OFFS) 117*2a61eff6SStefan Roese #define EBI_DEV2_TIM1_WR2_OFFS 0x00000230 118*2a61eff6SStefan Roese #define EBI_DEV2_TIM1_WR2(base) ((base) + EBI_DEV2_TIM1_WR2_OFFS) 119*2a61eff6SStefan Roese #define EBI_DEV2_TIM_EXT_OFFS 0x00000234 120*2a61eff6SStefan Roese #define EBI_DEV2_TIM_EXT(base) ((base) + EBI_DEV2_TIM_EXT_OFFS) 121*2a61eff6SStefan Roese #define EBI_DEV2_TIM2_CFI_RD1_OFFS 0x00000238 122*2a61eff6SStefan Roese #define EBI_DEV2_TIM2_CFI_RD1(base) ((base) + EBI_DEV2_TIM2_CFI_RD1_OFFS) 123*2a61eff6SStefan Roese #define EBI_DEV2_TIM2_CFI_RD2_OFFS 0x0000023C 124*2a61eff6SStefan Roese #define EBI_DEV2_TIM2_CFI_RD2(base) ((base) + EBI_DEV2_TIM2_CFI_RD2_OFFS) 125*2a61eff6SStefan Roese #define EBI_DEV2_TIM3_DMA1_OFFS 0x00000240 126*2a61eff6SStefan Roese #define EBI_DEV2_TIM3_DMA1(base) ((base) + EBI_DEV2_TIM3_DMA1_OFFS) 127*2a61eff6SStefan Roese #define EBI_DEV2_TIM3_DMA2_OFFS 0x00000244 128*2a61eff6SStefan Roese #define EBI_DEV2_TIM3_DMA2(base) ((base) + EBI_DEV2_TIM3_DMA2_OFFS) 129*2a61eff6SStefan Roese #define EBI_DEV2_ACK_RM_CNT_OFFS 0x00000250 130*2a61eff6SStefan Roese #define EBI_DEV2_ACK_RM_CNT(base) ((base) + EBI_DEV2_ACK_RM_CNT_OFFS) 131*2a61eff6SStefan Roese #define EBI_DEV3_DMA_EXT_ADDR_OFFS 0x00000300 132*2a61eff6SStefan Roese #define EBI_DEV3_DMA_EXT_ADDR(base) ((base) + EBI_DEV3_DMA_EXT_ADDR_OFFS) 133*2a61eff6SStefan Roese #define EBI_DEV3_EXT_ACC_OFFS 0x00000304 134*2a61eff6SStefan Roese #define EBI_DEV3_EXT_ACC(base) ((base) + EBI_DEV3_EXT_ACC_OFFS) 135*2a61eff6SStefan Roese #define EBI_DEV3_CONFIG1_OFFS 0x00000308 136*2a61eff6SStefan Roese #define EBI_DEV3_CONFIG1(base) ((base) + EBI_DEV3_CONFIG1_OFFS) 137*2a61eff6SStefan Roese #define EBI_DEV3_CONFIG2_OFFS 0x0000030C 138*2a61eff6SStefan Roese #define EBI_DEV3_CONFIG2(base) ((base) + EBI_DEV3_CONFIG2_OFFS) 139*2a61eff6SStefan Roese #define EBI_DEV3_FIFO_CONFIG_OFFS 0x00000310 140*2a61eff6SStefan Roese #define EBI_DEV3_FIFO_CONFIG(base) ((base) + EBI_DEV3_FIFO_CONFIG_OFFS) 141*2a61eff6SStefan Roese #define EBI_DEV3_FLASH_CONF_ST_OFFS 0x00000314 142*2a61eff6SStefan Roese #define EBI_DEV3_FLASH_CONF_ST(base) ((base) + EBI_DEV3_FLASH_CONF_ST_OFFS) 143*2a61eff6SStefan Roese #define EBI_DEV3_DMA_CONFIG1_OFFS 0x00000318 144*2a61eff6SStefan Roese #define EBI_DEV3_DMA_CONFIG1(base) ((base) + EBI_DEV3_DMA_CONFIG1_OFFS) 145*2a61eff6SStefan Roese #define EBI_DEV3_DMA_CONFIG2_OFFS 0x0000031C 146*2a61eff6SStefan Roese #define EBI_DEV3_DMA_CONFIG2(base) ((base) + EBI_DEV3_DMA_CONFIG2_OFFS) 147*2a61eff6SStefan Roese #define EBI_DEV3_TIM1_RD1_OFFS 0x00000324 148*2a61eff6SStefan Roese #define EBI_DEV3_TIM1_RD1(base) ((base) + EBI_DEV3_TIM1_RD1_OFFS) 149*2a61eff6SStefan Roese #define EBI_DEV3_TIM1_RD2_OFFS 0x00000328 150*2a61eff6SStefan Roese #define EBI_DEV3_TIM1_RD2(base) ((base) + EBI_DEV3_TIM1_RD2_OFFS) 151*2a61eff6SStefan Roese #define EBI_DEV3_TIM1_WR1_OFFS 0x0000032C 152*2a61eff6SStefan Roese #define EBI_DEV3_TIM1_WR1(base) ((base) + EBI_DEV3_TIM1_WR1_OFFS) 153*2a61eff6SStefan Roese #define EBI_DEV3_TIM1_WR2_OFFS 0x00000330 154*2a61eff6SStefan Roese #define EBI_DEV3_TIM1_WR2(base) ((base) + EBI_DEV3_TIM1_WR2_OFFS) 155*2a61eff6SStefan Roese #define EBI_DEV3_TIM_EXT_OFFS 0x00000334 156*2a61eff6SStefan Roese #define EBI_DEV3_TIM_EXT(base) ((base) + EBI_DEV3_TIM_EXT_OFFS) 157*2a61eff6SStefan Roese #define EBI_DEV3_TIM2_CFI_RD1_OFFS 0x00000338 158*2a61eff6SStefan Roese #define EBI_DEV3_TIM2_CFI_RD1(base) ((base) + EBI_DEV3_TIM2_CFI_RD1_OFFS) 159*2a61eff6SStefan Roese #define EBI_DEV3_TIM2_CFI_RD2_OFFS 0x0000033C 160*2a61eff6SStefan Roese #define EBI_DEV3_TIM2_CFI_RD2(base) ((base) + EBI_DEV3_TIM2_CFI_RD2_OFFS) 161*2a61eff6SStefan Roese #define EBI_DEV3_TIM3_DMA1_OFFS 0x00000340 162*2a61eff6SStefan Roese #define EBI_DEV3_TIM3_DMA1(base) ((base) + EBI_DEV3_TIM3_DMA1_OFFS) 163*2a61eff6SStefan Roese #define EBI_DEV3_TIM3_DMA2_OFFS 0x00000344 164*2a61eff6SStefan Roese #define EBI_DEV3_TIM3_DMA2(base) ((base) + EBI_DEV3_TIM3_DMA2_OFFS) 165*2a61eff6SStefan Roese #define EBI_DEV3_ACK_RM_CNT_OFFS 0x00000350 166*2a61eff6SStefan Roese #define EBI_DEV3_ACK_RM_CNT(base) ((base) + EBI_DEV3_ACK_RM_CNT_OFFS) 167*2a61eff6SStefan Roese #define EBI_DEV4_DMA_EXT_ADDR_OFFS 0x00000400 168*2a61eff6SStefan Roese #define EBI_DEV4_DMA_EXT_ADDR(base) ((base) + EBI_DEV4_DMA_EXT_ADDR_OFFS) 169*2a61eff6SStefan Roese #define EBI_DEV4_EXT_ACC_OFFS 0x00000404 170*2a61eff6SStefan Roese #define EBI_DEV4_EXT_ACC(base) ((base) + EBI_DEV4_EXT_ACC_OFFS) 171*2a61eff6SStefan Roese #define EBI_DEV4_CONFIG1_OFFS 0x00000408 172*2a61eff6SStefan Roese #define EBI_DEV4_CONFIG1(base) ((base) + EBI_DEV4_CONFIG1_OFFS) 173*2a61eff6SStefan Roese #define EBI_DEV4_CONFIG2_OFFS 0x0000040C 174*2a61eff6SStefan Roese #define EBI_DEV4_CONFIG2(base) ((base) + EBI_DEV4_CONFIG2_OFFS) 175*2a61eff6SStefan Roese #define EBI_DEV4_FIFO_CONFIG_OFFS 0x00000410 176*2a61eff6SStefan Roese #define EBI_DEV4_FIFO_CONFIG(base) ((base) + EBI_DEV4_FIFO_CONFIG_OFFS) 177*2a61eff6SStefan Roese #define EBI_DEV4_FLASH_CONF_ST_OFFS 0x00000414 178*2a61eff6SStefan Roese #define EBI_DEV4_FLASH_CONF_ST(base) ((base) + EBI_DEV4_FLASH_CONF_ST_OFFS) 179*2a61eff6SStefan Roese #define EBI_DEV4_DMA_CONFIG1_OFFS 0x00000418 180*2a61eff6SStefan Roese #define EBI_DEV4_DMA_CONFIG1(base) ((base) + EBI_DEV4_DMA_CONFIG1_OFFS) 181*2a61eff6SStefan Roese #define EBI_DEV4_DMA_CONFIG2_OFFS 0x0000041C 182*2a61eff6SStefan Roese #define EBI_DEV4_DMA_CONFIG2(base) ((base) + EBI_DEV4_DMA_CONFIG2_OFFS) 183*2a61eff6SStefan Roese #define EBI_DEV4_TIM1_RD1_OFFS 0x00000424 184*2a61eff6SStefan Roese #define EBI_DEV4_TIM1_RD1(base) ((base) + EBI_DEV4_TIM1_RD1_OFFS) 185*2a61eff6SStefan Roese #define EBI_DEV4_TIM1_RD2_OFFS 0x00000428 186*2a61eff6SStefan Roese #define EBI_DEV4_TIM1_RD2(base) ((base) + EBI_DEV4_TIM1_RD2_OFFS) 187*2a61eff6SStefan Roese #define EBI_DEV4_TIM1_WR1_OFFS 0x0000042C 188*2a61eff6SStefan Roese #define EBI_DEV4_TIM1_WR1(base) ((base) + EBI_DEV4_TIM1_WR1_OFFS) 189*2a61eff6SStefan Roese #define EBI_DEV4_TIM1_WR2_OFFS 0x00000430 190*2a61eff6SStefan Roese #define EBI_DEV4_TIM1_WR2(base) ((base) + EBI_DEV4_TIM1_WR2_OFFS) 191*2a61eff6SStefan Roese #define EBI_DEV4_TIM_EXT_OFFS 0x00000434 192*2a61eff6SStefan Roese #define EBI_DEV4_TIM_EXT(base) ((base) + EBI_DEV4_TIM_EXT_OFFS) 193*2a61eff6SStefan Roese #define EBI_DEV4_TIM2_CFI_RD1_OFFS 0x00000438 194*2a61eff6SStefan Roese #define EBI_DEV4_TIM2_CFI_RD1(base) ((base) + EBI_DEV4_TIM2_CFI_RD1_OFFS) 195*2a61eff6SStefan Roese #define EBI_DEV4_TIM2_CFI_RD2_OFFS 0x0000043C 196*2a61eff6SStefan Roese #define EBI_DEV4_TIM2_CFI_RD2(base) ((base) + EBI_DEV4_TIM2_CFI_RD2_OFFS) 197*2a61eff6SStefan Roese #define EBI_DEV4_TIM3_DMA1_OFFS 0x00000440 198*2a61eff6SStefan Roese #define EBI_DEV4_TIM3_DMA1(base) ((base) + EBI_DEV4_TIM3_DMA1_OFFS) 199*2a61eff6SStefan Roese #define EBI_DEV4_TIM3_DMA2_OFFS 0x00000444 200*2a61eff6SStefan Roese #define EBI_DEV4_TIM3_DMA2(base) ((base) + EBI_DEV4_TIM3_DMA2_OFFS) 201*2a61eff6SStefan Roese #define EBI_DEV4_ACK_RM_CNT_OFFS 0x00000450 202*2a61eff6SStefan Roese #define EBI_DEV4_ACK_RM_CNT(base) ((base) + EBI_DEV4_ACK_RM_CNT_OFFS) 203*2a61eff6SStefan Roese #define EBI_CNT_FL_PROGR_OFFS 0x00000904 204*2a61eff6SStefan Roese #define EBI_CNT_FL_PROGR(base) ((base) + EBI_CNT_FL_PROGR_OFFS) 205*2a61eff6SStefan Roese #define EBI_CNT_EXT_PAGE_SZ_OFFS 0x0000090C 206*2a61eff6SStefan Roese #define EBI_CNT_EXT_PAGE_SZ(base) ((base) + EBI_CNT_EXT_PAGE_SZ_OFFS) 207*2a61eff6SStefan Roese #define EBI_CNT_WAIT_RDY_OFFS 0x00000914 208*2a61eff6SStefan Roese #define EBI_CNT_WAIT_RDY(base) ((base) + EBI_CNT_WAIT_RDY_OFFS) 209*2a61eff6SStefan Roese #define EBI_CNT_ACK_OFFS 0x00000918 210*2a61eff6SStefan Roese #define EBI_CNT_ACK(base) ((base) + EBI_CNT_ACK_OFFS) 211*2a61eff6SStefan Roese #define EBI_GENIO1_CONFIG1_OFFS 0x00000A00 212*2a61eff6SStefan Roese #define EBI_GENIO1_CONFIG1(base) ((base) + EBI_GENIO1_CONFIG1_OFFS) 213*2a61eff6SStefan Roese #define EBI_GENIO1_CONFIG2_OFFS 0x00000A04 214*2a61eff6SStefan Roese #define EBI_GENIO1_CONFIG2(base) ((base) + EBI_GENIO1_CONFIG2_OFFS) 215*2a61eff6SStefan Roese #define EBI_GENIO1_CONFIG3_OFFS 0x00000A08 216*2a61eff6SStefan Roese #define EBI_GENIO1_CONFIG3(base) ((base) + EBI_GENIO1_CONFIG3_OFFS) 217*2a61eff6SStefan Roese #define EBI_GENIO2_CONFIG1_OFFS 0x00000A10 218*2a61eff6SStefan Roese #define EBI_GENIO2_CONFIG1(base) ((base) + EBI_GENIO2_CONFIG1_OFFS) 219*2a61eff6SStefan Roese #define EBI_GENIO2_CONFIG2_OFFS 0x00000A14 220*2a61eff6SStefan Roese #define EBI_GENIO2_CONFIG2(base) ((base) + EBI_GENIO2_CONFIG2_OFFS) 221*2a61eff6SStefan Roese #define EBI_GENIO2_CONFIG3_OFFS 0x00000A18 222*2a61eff6SStefan Roese #define EBI_GENIO2_CONFIG3(base) ((base) + EBI_GENIO2_CONFIG3_OFFS) 223*2a61eff6SStefan Roese #define EBI_GENIO3_CONFIG1_OFFS 0x00000A20 224*2a61eff6SStefan Roese #define EBI_GENIO3_CONFIG1(base) ((base) + EBI_GENIO3_CONFIG1_OFFS) 225*2a61eff6SStefan Roese #define EBI_GENIO3_CONFIG2_OFFS 0x00000A24 226*2a61eff6SStefan Roese #define EBI_GENIO3_CONFIG2(base) ((base) + EBI_GENIO3_CONFIG2_OFFS) 227*2a61eff6SStefan Roese #define EBI_GENIO3_CONFIG3_OFFS 0x00000A28 228*2a61eff6SStefan Roese #define EBI_GENIO3_CONFIG3(base) ((base) + EBI_GENIO3_CONFIG3_OFFS) 229*2a61eff6SStefan Roese #define EBI_GENIO4_CONFIG1_OFFS 0x00000A30 230*2a61eff6SStefan Roese #define EBI_GENIO4_CONFIG1(base) ((base) + EBI_GENIO4_CONFIG1_OFFS) 231*2a61eff6SStefan Roese #define EBI_GENIO4_CONFIG2_OFFS 0x00000A34 232*2a61eff6SStefan Roese #define EBI_GENIO4_CONFIG2(base) ((base) + EBI_GENIO4_CONFIG2_OFFS) 233*2a61eff6SStefan Roese #define EBI_GENIO4_CONFIG3_OFFS 0x00000A38 234*2a61eff6SStefan Roese #define EBI_GENIO4_CONFIG3(base) ((base) + EBI_GENIO4_CONFIG3_OFFS) 235*2a61eff6SStefan Roese #define EBI_GENIO5_CONFIG1_OFFS 0x00000A40 236*2a61eff6SStefan Roese #define EBI_GENIO5_CONFIG1(base) ((base) + EBI_GENIO5_CONFIG1_OFFS) 237*2a61eff6SStefan Roese #define EBI_GENIO5_CONFIG2_OFFS 0x00000A44 238*2a61eff6SStefan Roese #define EBI_GENIO5_CONFIG2(base) ((base) + EBI_GENIO5_CONFIG2_OFFS) 239*2a61eff6SStefan Roese #define EBI_GENIO5_CONFIG3_OFFS 0x00000A48 240*2a61eff6SStefan Roese #define EBI_GENIO5_CONFIG3(base) ((base) + EBI_GENIO5_CONFIG3_OFFS) 241*2a61eff6SStefan Roese 242*2a61eff6SStefan Roese #endif 243