150752790SStefan Roese /* 250752790SStefan Roese * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering 350752790SStefan Roese * 4*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 550752790SStefan Roese */ 650752790SStefan Roese 750752790SStefan Roese #ifndef __EBI__ 850752790SStefan Roese #define __EBI__ 950752790SStefan Roese 1050752790SStefan Roese #include <common.h> 1150752790SStefan Roese #include <asm/io.h> 1250752790SStefan Roese #include "vct.h" 1350752790SStefan Roese 1450752790SStefan Roese #define EXT_DEVICE_CHANNEL_3 (0x30000000) 1550752790SStefan Roese #define EXT_DEVICE_CHANNEL_2 (0x20000000) 1650752790SStefan Roese #define EXT_DEVICE_CHANNEL_1 (0x10000000) 1750752790SStefan Roese #define EXT_CPU_ACCESS_ACTIVE (0x00000001) 1850752790SStefan Roese #define EXT_DMA_ACCESS_ACTIVE (1 << 14) 1950752790SStefan Roese #define EXT_CPU_IORDY_SL (0x00000001) 2050752790SStefan Roese 2150752790SStefan Roese #define EBI_CPU_WRITE (1 << 31) 2250752790SStefan Roese #define EBI_CPU_ID_SHIFT (28) 2350752790SStefan Roese #define EBI_CPU_ADDR_MASK ~(~0UL << EBI_CPU_ID_SHIFT) 2450752790SStefan Roese 2550752790SStefan Roese /* position of various bit slices in timing register EBI_DEV[01]_TIM1_RD1 */ 2650752790SStefan Roese #define ADDR_LATCH_ENABLE 0 2750752790SStefan Roese #define ADDR_ACTIVATION 4 2850752790SStefan Roese #define CHIP_SELECT_START 8 2950752790SStefan Roese #define OUTPUT_ENABLE_START 12 3050752790SStefan Roese #define WAIT_TIME 28 3150752790SStefan Roese #define READ_DURATION 20 3250752790SStefan Roese 3350752790SStefan Roese /* position of various bit slices in timing register EBI_DEV[01]_TIM1_RD2 */ 3450752790SStefan Roese #define OUTPUT_ENABLE_END 0 3550752790SStefan Roese #define CHIP_SELECT_END 4 3650752790SStefan Roese #define ADDR_DEACTIVATION 8 3750752790SStefan Roese #define RECOVER_TIME 12 3850752790SStefan Roese #define ACK_TIME 20 3950752790SStefan Roese 4050752790SStefan Roese /* various bits in configuration register EBI_DEV[01]_CONFIG1 */ 4150752790SStefan Roese #define EBI_EXTERNAL_DATA_8 (1 << 8) 4250752790SStefan Roese #define EBI_EXT_ADDR_SHIFT (1 << 22) 4350752790SStefan Roese #define EBI_EXTERNAL_DATA_16 EBI_EXT_ADDR_SHIFT 4450752790SStefan Roese #define EBI_CHIP_SELECT_1 0x2 4550752790SStefan Roese #define EBI_CHIP_SELECT_2 0x4 4650752790SStefan Roese #define EBI_BUSY_EN_RD (1 << 12) 4750752790SStefan Roese #define DIR_ACCESS_WRITE (1 << 20) 4850752790SStefan Roese #define DIR_ACCESS_MASK (1 << 20) 4950752790SStefan Roese 5050752790SStefan Roese /* various bits in configuration register EBI_DEV[01]_CONFIG2 */ 5150752790SStefan Roese #define ADDRESS_INCREMENT_ON 0x0 5250752790SStefan Roese #define ADDRESS_INCREMENT_OFF 0x100 5350752790SStefan Roese #define QUEUE_LENGTH_1 0x40 5450752790SStefan Roese #define QUEUE_LENGTH_2 0x80 5550752790SStefan Roese #define QUEUE_LENGTH_3 0xC0 5650752790SStefan Roese #define QUEUE_LENGTH_4 0 5750752790SStefan Roese #define CPU_TRANSFER_SIZE_32 0 5850752790SStefan Roese #define CPU_TRANSFER_SIZE_16 0x10 5950752790SStefan Roese #define CPU_TRANSFER_SIZE_8 0x20 6050752790SStefan Roese #define READ_ENDIANNESS_ABCD 0 6150752790SStefan Roese #define READ_ENDIANNESS_DCBA 0x4 6250752790SStefan Roese #define READ_ENDIANNESS_BADC 0x8 6350752790SStefan Roese #define READ_ENDIANNESS_CDAB 0xC 6450752790SStefan Roese #define WRITE_ENDIANNESS_ABCD 0 6550752790SStefan Roese #define WRITE_ENDIANNESS_DCBA 0x1 6650752790SStefan Roese #define WRITE_ENDIANNESS_BADC 0x2 6750752790SStefan Roese #define WRITE_ENDIANNESS_CDAB 0x3 6850752790SStefan Roese 6950752790SStefan Roese /* various bits in configuration register EBI_CTRL_SIG_ACTLV */ 7050752790SStefan Roese #define IORDY_ACTIVELEVEL_HIGH (1 << 14) 7150752790SStefan Roese #define ALE_ACTIVELEVEL_HIGH (1 << 8) 7250752790SStefan Roese 7350752790SStefan Roese /* bits in register EBI_SIG_LEVEL */ 7450752790SStefan Roese #define IORDY_LEVEL_MASK 1 7550752790SStefan Roese ebi_wait(void)7650752790SStefan Roesestatic inline void ebi_wait(void) 7750752790SStefan Roese { 7850752790SStefan Roese while (reg_read(EBI_STATUS(EBI_BASE)) & EXT_CPU_ACCESS_ACTIVE) 7950752790SStefan Roese ; /* wait */ 8050752790SStefan Roese } 8150752790SStefan Roese 8250752790SStefan Roese #endif 83