1a4884831SStefan Roese /* 2a4884831SStefan Roese * Copyright (C) 2014 Stefan Roese <sr@denx.de> 3a4884831SStefan Roese * 4a4884831SStefan Roese * SPDX-License-Identifier: GPL-2.0+ 5a4884831SStefan Roese */ 6a4884831SStefan Roese 7a4884831SStefan Roese #include <common.h> 8a4884831SStefan Roese #include <miiphy.h> 9a4884831SStefan Roese #include <asm/io.h> 10a4884831SStefan Roese #include <asm/arch/cpu.h> 11a4884831SStefan Roese #include <asm/arch/soc.h> 12a4884831SStefan Roese #include <linux/mbus.h> 13a4884831SStefan Roese 1429b103c7SStefan Roese #include "../drivers/ddr/marvell/axp/ddr3_hw_training.h" 1529b103c7SStefan Roese #include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h" 16e7778ec1SStefan Roese 17a4884831SStefan Roese DECLARE_GLOBAL_DATA_PTR; 18a4884831SStefan Roese 19a4884831SStefan Roese /* Base addresses for the external device chip selects */ 20a4884831SStefan Roese #define DEV_CS0_BASE 0xe0000000 21a4884831SStefan Roese #define DEV_CS1_BASE 0xe1000000 22a4884831SStefan Roese #define DEV_CS2_BASE 0xe2000000 23a4884831SStefan Roese #define DEV_CS3_BASE 0xe3000000 24a4884831SStefan Roese 25e7778ec1SStefan Roese /* DDR3 static configuration */ 26e7778ec1SStefan Roese MV_DRAM_MC_INIT ddr3_b0_maxbcm[MV_MAX_DDR3_STATIC_SIZE] = { 27e7778ec1SStefan Roese {0x00001400, 0x7301CC30}, /* DDR SDRAM Configuration Register */ 28e7778ec1SStefan Roese {0x00001404, 0x30000820}, /* Dunit Control Low Register */ 29e7778ec1SStefan Roese {0x00001408, 0x5515BAAB}, /* DDR SDRAM Timing (Low) Register */ 30e7778ec1SStefan Roese {0x0000140C, 0x38DA3F97}, /* DDR SDRAM Timing (High) Register */ 31e7778ec1SStefan Roese {0x00001410, 0x20100005}, /* DDR SDRAM Address Control Register */ 32e7778ec1SStefan Roese {0x00001414, 0x0000F3FF}, /* DDR SDRAM Open Pages Control Reg */ 33e7778ec1SStefan Roese {0x00001418, 0x00000e00}, /* DDR SDRAM Operation Register */ 34e7778ec1SStefan Roese {0x0000141C, 0x00000672}, /* DDR SDRAM Mode Register */ 35e7778ec1SStefan Roese {0x00001420, 0x00000004}, /* DDR SDRAM Extended Mode Register */ 36e7778ec1SStefan Roese {0x00001424, 0x0000F3FF}, /* Dunit Control High Register */ 37e7778ec1SStefan Roese {0x00001428, 0x0011A940}, /* Dunit Control High Register */ 38e7778ec1SStefan Roese {0x0000142C, 0x014C5134}, /* Dunit Control High Register */ 39e7778ec1SStefan Roese {0x0000147C, 0x0000D771}, 40e7778ec1SStefan Roese 41e7778ec1SStefan Roese {0x00001494, 0x00010000}, /* DDR SDRAM ODT Control (Low) Reg */ 42e7778ec1SStefan Roese {0x0000149C, 0x00000001}, /* DDR Dunit ODT Control Register */ 43e7778ec1SStefan Roese {0x000014A0, 0x00000001}, 44e7778ec1SStefan Roese {0x000014A8, 0x00000101}, 45e7778ec1SStefan Roese 46e7778ec1SStefan Roese /* Recommended Settings from Marvell for 4 x 16 bit devices: */ 47e7778ec1SStefan Roese {0x000014C0, 0x192424C9}, /* DRAM addr and Ctrl Driving Strenght*/ 48e7778ec1SStefan Roese {0x000014C4, 0xAAA24C9}, /* DRAM Data and DQS Driving Strenght */ 49e7778ec1SStefan Roese 50e7778ec1SStefan Roese /* 51e7778ec1SStefan Roese * DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the 52e7778ec1SStefan Roese * training sequence 53e7778ec1SStefan Roese */ 54e7778ec1SStefan Roese {0x000200e8, 0x3FFF0E01}, 55e7778ec1SStefan Roese {0x00020184, 0x3FFFFFE0}, /* Close fast path Window to - 2G */ 56e7778ec1SStefan Roese 57e7778ec1SStefan Roese {0x0001504, 0x3FFFFFE1}, /* CS0 Size */ 58e7778ec1SStefan Roese {0x000150C, 0x00000000}, /* CS1 Size */ 59e7778ec1SStefan Roese {0x0001514, 0x00000000}, /* CS2 Size */ 60e7778ec1SStefan Roese {0x000151C, 0x00000000}, /* CS3 Size */ 61e7778ec1SStefan Roese 62e7778ec1SStefan Roese {0x0020220, 0x00000007}, /* Reserved */ 63e7778ec1SStefan Roese 64e7778ec1SStefan Roese {0x00001538, 0x0000000B}, /* Read Data Sample Delays Register */ 65e7778ec1SStefan Roese {0x0000153C, 0x0000000B}, /* Read Data Ready Delay Register */ 66e7778ec1SStefan Roese 67e7778ec1SStefan Roese {0x000015D0, 0x00000670}, /* MR0 */ 68e7778ec1SStefan Roese {0x000015D4, 0x00000044}, /* MR1 */ 69e7778ec1SStefan Roese {0x000015D8, 0x00000018}, /* MR2 */ 70e7778ec1SStefan Roese {0x000015DC, 0x00000000}, /* MR3 */ 71e7778ec1SStefan Roese {0x000015E0, 0x00000001}, 72e7778ec1SStefan Roese {0x000015E4, 0x00203c18}, /* ZQDS Configuration Register */ 73e7778ec1SStefan Roese {0x000015EC, 0xF800A225}, /* DDR PHY */ 74e7778ec1SStefan Roese 75e7778ec1SStefan Roese {0x0, 0x0} 76e7778ec1SStefan Roese }; 77e7778ec1SStefan Roese 78e7778ec1SStefan Roese MV_DRAM_MODES maxbcm_ddr_modes[MV_DDR3_MODES_NUMBER] = { 79e7778ec1SStefan Roese {"maxbcm_1600-800", 0xB, 0x5, 0x0, A0, ddr3_b0_maxbcm, NULL}, 80e7778ec1SStefan Roese }; 81e7778ec1SStefan Roese 82e7778ec1SStefan Roese extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[]; 83e7778ec1SStefan Roese 84e7778ec1SStefan Roese /* MAXBCM: SERDES 0-4 PCIE, Serdes 7 = SGMII 0, all others = unconnected */ 85e7778ec1SStefan Roese MV_BIN_SERDES_CFG maxbcm_serdes_cfg[] = { 86e7778ec1SStefan Roese { MV_PEX_ROOT_COMPLEX, 0x20011111, 0x00000000, 87e7778ec1SStefan Roese { PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_DISABLED, 88e7778ec1SStefan Roese PEX_BUS_DISABLED }, 89e7778ec1SStefan Roese 0x1f, serdes_change_m_phy 90e7778ec1SStefan Roese } 91e7778ec1SStefan Roese }; 92e7778ec1SStefan Roese 93e7778ec1SStefan Roese MV_DRAM_MODES *ddr3_get_static_ddr_mode(void) 94e7778ec1SStefan Roese { 95e7778ec1SStefan Roese /* Only one mode supported for this board */ 96e7778ec1SStefan Roese return &maxbcm_ddr_modes[0]; 97e7778ec1SStefan Roese } 98e7778ec1SStefan Roese 99e7778ec1SStefan Roese MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode) 100e7778ec1SStefan Roese { 101e7778ec1SStefan Roese return &maxbcm_serdes_cfg[0]; 102e7778ec1SStefan Roese } 103a4884831SStefan Roese 104a4884831SStefan Roese int board_early_init_f(void) 105a4884831SStefan Roese { 106a4884831SStefan Roese /* 107a4884831SStefan Roese * Don't configure MPP (pin multiplexing) and GPIO here, 108a4884831SStefan Roese * its already done in bin_hdr 109a4884831SStefan Roese */ 110a4884831SStefan Roese 111a4884831SStefan Roese /* 112a4884831SStefan Roese * Setup some board specific mbus address windows 113a4884831SStefan Roese */ 114a4884831SStefan Roese mbus_dt_setup_win(&mbus_state, DEV_CS0_BASE, 16 << 20, 115a4884831SStefan Roese CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS0); 116a4884831SStefan Roese mbus_dt_setup_win(&mbus_state, DEV_CS1_BASE, 16 << 20, 117a4884831SStefan Roese CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS1); 118a4884831SStefan Roese mbus_dt_setup_win(&mbus_state, DEV_CS2_BASE, 16 << 20, 119a4884831SStefan Roese CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS2); 120a4884831SStefan Roese mbus_dt_setup_win(&mbus_state, DEV_CS3_BASE, 16 << 20, 121a4884831SStefan Roese CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS3); 122a4884831SStefan Roese 123a4884831SStefan Roese return 0; 124a4884831SStefan Roese } 125a4884831SStefan Roese 126a4884831SStefan Roese int board_init(void) 127a4884831SStefan Roese { 128a4884831SStefan Roese /* adress of boot parameters */ 129a4884831SStefan Roese gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; 130a4884831SStefan Roese 131a4884831SStefan Roese return 0; 132a4884831SStefan Roese } 133a4884831SStefan Roese 134a4884831SStefan Roese int checkboard(void) 135a4884831SStefan Roese { 136a4884831SStefan Roese puts("Board: maxBCM\n"); 137a4884831SStefan Roese 138a4884831SStefan Roese return 0; 139a4884831SStefan Roese } 140a4884831SStefan Roese 141a4884831SStefan Roese /* Configure and enable MV88E6185 switch */ 142*e3b9c98aSStefan Roese int board_phy_config(struct phy_device *phydev) 143a4884831SStefan Roese { 144*e3b9c98aSStefan Roese /* 145*e3b9c98aSStefan Roese * todo: 146*e3b9c98aSStefan Roese * Fill this with the real setup / config code. 147*e3b9c98aSStefan Roese * Please see board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c 148*e3b9c98aSStefan Roese * for details. 149*e3b9c98aSStefan Roese */ 150*e3b9c98aSStefan Roese printf("88E6185 Initialized\n"); 151*e3b9c98aSStefan Roese return 0; 152a4884831SStefan Roese } 153