1 /* 2 * Novena SPL 3 * 4 * Copyright (C) 2014 Marek Vasut <marex@denx.de> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/io.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/iomux.h> 13 #include <asm/arch/mx6-ddr.h> 14 #include <asm/arch/mx6-pins.h> 15 #include <asm/arch/sys_proto.h> 16 #include <asm/gpio.h> 17 #include <asm/imx-common/boot_mode.h> 18 #include <asm/imx-common/iomux-v3.h> 19 #include <asm/imx-common/mxc_i2c.h> 20 #include <i2c.h> 21 #include <mmc.h> 22 #include <fsl_esdhc.h> 23 #include <spl.h> 24 25 #include <asm/arch/mx6-ddr.h> 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 #define UART_PAD_CTRL \ 30 (PAD_CTL_PKE | PAD_CTL_PUE | \ 31 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 32 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 33 34 #define USDHC_PAD_CTRL \ 35 (PAD_CTL_PKE | PAD_CTL_PUE | \ 36 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ 37 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 38 39 #define ENET_PAD_CTRL \ 40 (PAD_CTL_PKE | PAD_CTL_PUE | \ 41 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 42 PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 43 44 #define RGMII_PAD_CTRL \ 45 (PAD_CTL_PKE | PAD_CTL_PUE | \ 46 PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 47 48 #define SPI_PAD_CTRL \ 49 (PAD_CTL_HYS | \ 50 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ 51 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 52 53 #define I2C_PAD_CTRL \ 54 (PAD_CTL_PKE | PAD_CTL_PUE | \ 55 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ 56 PAD_CTL_DSE_240ohm | PAD_CTL_HYS | \ 57 PAD_CTL_ODE) 58 59 #define BUTTON_PAD_CTRL \ 60 (PAD_CTL_PKE | PAD_CTL_PUE | \ 61 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 62 PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 63 64 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 65 66 #define NOVENA_AUDIO_PWRON IMX_GPIO_NR(5, 17) 67 #define NOVENA_FPGA_RESET_N_GPIO IMX_GPIO_NR(5, 7) 68 #define NOVENA_HDMI_GHOST_HPD IMX_GPIO_NR(5, 4) 69 #define NOVENA_PCIE_RESET_GPIO IMX_GPIO_NR(3, 29) 70 #define NOVENA_PCIE_POWER_ON_GPIO IMX_GPIO_NR(7, 12) 71 #define NOVENA_PCIE_WAKE_UP_GPIO IMX_GPIO_NR(3, 22) 72 #define NOVENA_PCIE_DISABLE_GPIO IMX_GPIO_NR(2, 16) 73 74 /* 75 * Audio 76 */ 77 static iomux_v3_cfg_t audio_pads[] = { 78 /* AUD_PWRON */ 79 MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), 80 }; 81 82 static void novena_spl_setup_iomux_audio(void) 83 { 84 imx_iomux_v3_setup_multiple_pads(audio_pads, ARRAY_SIZE(audio_pads)); 85 gpio_direction_output(NOVENA_AUDIO_PWRON, 1); 86 } 87 88 /* 89 * ENET 90 */ 91 static iomux_v3_cfg_t enet_pads1[] = { 92 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 93 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 94 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(RGMII_PAD_CTRL), 95 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(RGMII_PAD_CTRL), 96 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(RGMII_PAD_CTRL), 97 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(RGMII_PAD_CTRL), 98 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(RGMII_PAD_CTRL), 99 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(RGMII_PAD_CTRL), 100 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 101 /* pin 35 - 1 (PHY_AD2) on reset */ 102 MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), 103 /* pin 32 - 1 - (MODE0) all */ 104 MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), 105 /* pin 31 - 1 - (MODE1) all */ 106 MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), 107 /* pin 28 - 1 - (MODE2) all */ 108 MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), 109 /* pin 27 - 1 - (MODE3) all */ 110 MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), 111 /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ 112 MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL), 113 /* pin 42 PHY nRST */ 114 MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), 115 }; 116 117 static iomux_v3_cfg_t enet_pads2[] = { 118 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(RGMII_PAD_CTRL), 119 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(RGMII_PAD_CTRL), 120 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(RGMII_PAD_CTRL), 121 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(RGMII_PAD_CTRL), 122 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(RGMII_PAD_CTRL), 123 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(RGMII_PAD_CTRL), 124 }; 125 126 static void novena_spl_setup_iomux_enet(void) 127 { 128 imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); 129 130 gpio_direction_output(IMX_GPIO_NR(3, 23), 0); 131 gpio_direction_output(IMX_GPIO_NR(6, 30), 1); 132 gpio_direction_output(IMX_GPIO_NR(6, 25), 1); 133 gpio_direction_output(IMX_GPIO_NR(6, 27), 1); 134 gpio_direction_output(IMX_GPIO_NR(6, 28), 1); 135 gpio_direction_output(IMX_GPIO_NR(6, 29), 1); 136 gpio_direction_output(IMX_GPIO_NR(6, 24), 1); 137 138 imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); 139 } 140 141 /* 142 * FPGA 143 */ 144 static iomux_v3_cfg_t fpga_pads[] = { 145 /* FPGA_RESET_N */ 146 MX6_PAD_DISP0_DAT13__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), 147 }; 148 149 static void novena_spl_setup_iomux_fpga(void) 150 { 151 imx_iomux_v3_setup_multiple_pads(fpga_pads, ARRAY_SIZE(fpga_pads)); 152 gpio_direction_output(NOVENA_FPGA_RESET_N_GPIO, 0); 153 } 154 155 /* 156 * GPIO Button 157 */ 158 static iomux_v3_cfg_t button_pads[] = { 159 /* Debug */ 160 MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), 161 }; 162 163 static void novena_spl_setup_iomux_buttons(void) 164 { 165 imx_iomux_v3_setup_multiple_pads(button_pads, ARRAY_SIZE(button_pads)); 166 } 167 168 /* 169 * I2C 170 */ 171 /* 172 * I2C1: 173 * 0x1d ... MMA7455L 174 * 0x30 ... SO-DIMM temp sensor 175 * 0x44 ... STMPE610 176 * 0x50 ... SO-DIMM ID 177 */ 178 struct i2c_pads_info i2c_pad_info0 = { 179 .scl = { 180 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, 181 .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC, 182 .gp = IMX_GPIO_NR(3, 21) 183 }, 184 .sda = { 185 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, 186 .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC, 187 .gp = IMX_GPIO_NR(3, 28) 188 } 189 }; 190 191 /* 192 * I2C2: 193 * 0x08 ... PMIC 194 * 0x3a ... HDMI DCC 195 * 0x50 ... HDMI DCC 196 */ 197 static struct i2c_pads_info i2c_pad_info1 = { 198 .scl = { 199 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC, 200 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, 201 .gp = IMX_GPIO_NR(2, 30) 202 }, 203 .sda = { 204 .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC, 205 .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC, 206 .gp = IMX_GPIO_NR(3, 16) 207 } 208 }; 209 210 /* 211 * I2C3: 212 * 0x11 ... ES8283 213 * 0x50 ... LCD EDID 214 * 0x56 ... EEPROM 215 */ 216 static struct i2c_pads_info i2c_pad_info2 = { 217 .scl = { 218 .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC, 219 .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC, 220 .gp = IMX_GPIO_NR(3, 17) 221 }, 222 .sda = { 223 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, 224 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, 225 .gp = IMX_GPIO_NR(3, 18) 226 } 227 }; 228 229 static void novena_spl_setup_iomux_i2c(void) 230 { 231 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); 232 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 233 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); 234 } 235 236 /* 237 * PCI express 238 */ 239 #ifdef CONFIG_CMD_PCI 240 static iomux_v3_cfg_t pcie_pads[] = { 241 /* "Reset" pin */ 242 MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), 243 /* "Power on" pin */ 244 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), 245 /* "Wake up" pin (input) */ 246 MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), 247 /* "Disable endpoint" (rfkill) pin */ 248 MX6_PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), 249 }; 250 251 static void novena_spl_setup_iomux_pcie(void) 252 { 253 imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); 254 255 /* Ensure PCIe is powered down */ 256 gpio_direction_output(NOVENA_PCIE_POWER_ON_GPIO, 0); 257 258 /* Put the card into reset */ 259 gpio_direction_output(NOVENA_PCIE_RESET_GPIO, 0); 260 261 /* Input signal to wake system from mPCIe card */ 262 gpio_direction_input(NOVENA_PCIE_WAKE_UP_GPIO); 263 264 /* Drive RFKILL high, to ensure the radio is turned on */ 265 gpio_direction_output(NOVENA_PCIE_DISABLE_GPIO, 1); 266 } 267 #else 268 static inline void novena_spl_setup_iomux_pcie(void) {} 269 #endif 270 271 /* 272 * SDHC 273 */ 274 static iomux_v3_cfg_t usdhc2_pads[] = { 275 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 276 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 277 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 278 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 279 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 280 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 281 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */ 282 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 283 }; 284 285 static iomux_v3_cfg_t usdhc3_pads[] = { 286 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 287 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 288 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 289 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 290 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 291 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 292 }; 293 294 static void novena_spl_setup_iomux_sdhc(void) 295 { 296 imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 297 imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 298 299 /* Big SD write-protect and card-detect */ 300 gpio_direction_input(IMX_GPIO_NR(1, 2)); 301 gpio_direction_input(IMX_GPIO_NR(1, 4)); 302 } 303 304 /* 305 * SPI 306 */ 307 #ifdef CONFIG_MXC_SPI 308 static iomux_v3_cfg_t ecspi3_pads[] = { 309 /* SS1 */ 310 MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), 311 MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), 312 MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), 313 MX6_PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(SPI_PAD_CTRL), 314 MX6_PAD_DISP0_DAT4__GPIO4_IO25 | MUX_PAD_CTRL(SPI_PAD_CTRL), 315 MX6_PAD_DISP0_DAT5__GPIO4_IO26 | MUX_PAD_CTRL(SPI_PAD_CTRL), 316 MX6_PAD_DISP0_DAT7__ECSPI3_RDY | MUX_PAD_CTRL(SPI_PAD_CTRL), 317 }; 318 319 static void novena_spl_setup_iomux_spi(void) 320 { 321 imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads)); 322 /* De-assert the nCS */ 323 gpio_direction_output(MX6_PAD_DISP0_DAT3__GPIO4_IO24, 1); 324 gpio_direction_output(MX6_PAD_DISP0_DAT4__GPIO4_IO25, 1); 325 gpio_direction_output(MX6_PAD_DISP0_DAT5__GPIO4_IO26, 1); 326 } 327 #else 328 static void novena_spl_setup_iomux_spi(void) {} 329 #endif 330 331 /* 332 * UART 333 */ 334 static iomux_v3_cfg_t const uart2_pads[] = { 335 MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 336 MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 337 }; 338 339 static iomux_v3_cfg_t const uart3_pads[] = { 340 MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 341 MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 342 }; 343 344 static iomux_v3_cfg_t const uart4_pads[] = { 345 MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 346 MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 347 MX6_PAD_CSI0_DAT16__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), 348 MX6_PAD_CSI0_DAT17__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), 349 350 }; 351 352 static void novena_spl_setup_iomux_uart(void) 353 { 354 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); 355 imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); 356 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); 357 } 358 359 /* 360 * Video 361 */ 362 #ifdef CONFIG_VIDEO 363 static iomux_v3_cfg_t hdmi_pads[] = { 364 /* "Ghost HPD" pin */ 365 MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), 366 }; 367 368 static void novena_spl_setup_iomux_video(void) 369 { 370 imx_iomux_v3_setup_multiple_pads(hdmi_pads, ARRAY_SIZE(hdmi_pads)); 371 gpio_direction_input(NOVENA_HDMI_GHOST_HPD); 372 } 373 #else 374 static inline void novena_spl_setup_iomux_video(void) {} 375 #endif 376 377 /* 378 * SPL boots from uSDHC card 379 */ 380 #ifdef CONFIG_FSL_ESDHC 381 static struct fsl_esdhc_cfg usdhc_cfg = { 382 USDHC3_BASE_ADDR, 0, 4 383 }; 384 385 int board_mmc_getcd(struct mmc *mmc) 386 { 387 /* There is no CD for a microSD card, assume always present. */ 388 return 1; 389 } 390 391 int board_mmc_init(bd_t *bis) 392 { 393 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 394 return fsl_esdhc_initialize(bis, &usdhc_cfg); 395 } 396 #endif 397 398 /* Configure MX6Q/DUAL mmdc DDR io registers */ 399 static struct mx6dq_iomux_ddr_regs novena_ddr_ioregs = { 400 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ 401 .dram_sdclk_0 = 0x00020038, 402 .dram_sdclk_1 = 0x00020038, 403 .dram_cas = 0x00000038, 404 .dram_ras = 0x00000038, 405 .dram_reset = 0x00000038, 406 /* SDCKE[0:1]: 100k pull-up */ 407 .dram_sdcke0 = 0x00003000, 408 .dram_sdcke1 = 0x00003000, 409 /* SDBA2: pull-up disabled */ 410 .dram_sdba2 = 0x00000000, 411 /* SDODT[0:1]: 100k pull-up, 40 ohm */ 412 .dram_sdodt0 = 0x00000038, 413 .dram_sdodt1 = 0x00000038, 414 /* SDQS[0:7]: Differential input, 40 ohm */ 415 .dram_sdqs0 = 0x00000038, 416 .dram_sdqs1 = 0x00000038, 417 .dram_sdqs2 = 0x00000038, 418 .dram_sdqs3 = 0x00000038, 419 .dram_sdqs4 = 0x00000038, 420 .dram_sdqs5 = 0x00000038, 421 .dram_sdqs6 = 0x00000038, 422 .dram_sdqs7 = 0x00000038, 423 424 /* DQM[0:7]: Differential input, 40 ohm */ 425 .dram_dqm0 = 0x00000038, 426 .dram_dqm1 = 0x00000038, 427 .dram_dqm2 = 0x00000038, 428 .dram_dqm3 = 0x00000038, 429 .dram_dqm4 = 0x00000038, 430 .dram_dqm5 = 0x00000038, 431 .dram_dqm6 = 0x00000038, 432 .dram_dqm7 = 0x00000038, 433 }; 434 435 /* Configure MX6Q/DUAL mmdc GRP io registers */ 436 static struct mx6dq_iomux_grp_regs novena_grp_ioregs = { 437 /* DDR3 */ 438 .grp_ddr_type = 0x000c0000, 439 .grp_ddrmode_ctl = 0x00020000, 440 /* Disable DDR pullups */ 441 .grp_ddrpke = 0x00000000, 442 /* ADDR[00:16], SDBA[0:1]: 40 ohm */ 443 .grp_addds = 0x00000038, 444 /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ 445 .grp_ctlds = 0x00000038, 446 /* DATA[00:63]: Differential input, 40 ohm */ 447 .grp_ddrmode = 0x00020000, 448 .grp_b0ds = 0x00000038, 449 .grp_b1ds = 0x00000038, 450 .grp_b2ds = 0x00000038, 451 .grp_b3ds = 0x00000038, 452 .grp_b4ds = 0x00000038, 453 .grp_b5ds = 0x00000038, 454 .grp_b6ds = 0x00000038, 455 .grp_b7ds = 0x00000038, 456 }; 457 458 static struct mx6_mmdc_calibration novena_mmdc_calib = { 459 /* write leveling calibration determine */ 460 .p0_mpwldectrl0 = 0x00420048, 461 .p0_mpwldectrl1 = 0x006f0059, 462 .p1_mpwldectrl0 = 0x005a0104, 463 .p1_mpwldectrl1 = 0x01070113, 464 /* Read DQS Gating calibration */ 465 .p0_mpdgctrl0 = 0x437c040b, 466 .p0_mpdgctrl1 = 0x0413040e, 467 .p1_mpdgctrl0 = 0x444f0446, 468 .p1_mpdgctrl1 = 0x044d0422, 469 /* Read Calibration: DQS delay relative to DQ read access */ 470 .p0_mprddlctl = 0x4c424249, 471 .p1_mprddlctl = 0x4e48414f, 472 /* Write Calibration: DQ/DM delay relative to DQS write access */ 473 .p0_mpwrdlctl = 0x42414641, 474 .p1_mpwrdlctl = 0x46374b43, 475 }; 476 477 static struct mx6_ddr_sysinfo novena_ddr_info = { 478 /* Width of data bus: 0=16, 1=32, 2=64 */ 479 .dsize = 2, 480 /* Config for full 4GB range so that get_mem_size() works */ 481 .cs_density = 32, /* 32Gb per CS */ 482 /* Single chip select */ 483 .ncs = 1, 484 .cs1_mirror = 0, 485 .rtt_wr = 1, /* RTT_Wr = RZQ/4 */ 486 .rtt_nom = 2, /* RTT_Nom = RZQ/2 */ 487 .walat = 3, /* Write additional latency */ 488 .ralat = 7, /* Read additional latency */ 489 .mif3_mode = 3, /* Command prediction working mode */ 490 .bi_on = 1, /* Bank interleaving enabled */ 491 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 492 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 493 }; 494 495 static struct mx6_ddr3_cfg elpida_4gib_1600 = { 496 .mem_speed = 1600, 497 .density = 4, 498 .width = 64, 499 .banks = 8, 500 .rowaddr = 16, 501 .coladdr = 10, 502 .pagesz = 2, 503 .trcd = 1300, 504 .trcmin = 4900, 505 .trasmin = 3590, 506 }; 507 508 /* 509 * called from C runtime startup code (arch/arm/lib/crt0.S:_main) 510 * - we have a stack and a place to store GD, both in SRAM 511 * - no variable global data is available 512 */ 513 void board_init_f(ulong dummy) 514 { 515 /* setup AIPS and disable watchdog */ 516 arch_cpu_init(); 517 518 /* setup GP timer */ 519 timer_init(); 520 521 #ifdef CONFIG_BOARD_POSTCLK_INIT 522 board_postclk_init(); 523 #endif 524 #ifdef CONFIG_FSL_ESDHC 525 get_clocks(); 526 #endif 527 528 /* Setup IOMUX and configure basics. */ 529 novena_spl_setup_iomux_audio(); 530 novena_spl_setup_iomux_buttons(); 531 novena_spl_setup_iomux_enet(); 532 novena_spl_setup_iomux_fpga(); 533 novena_spl_setup_iomux_i2c(); 534 novena_spl_setup_iomux_pcie(); 535 novena_spl_setup_iomux_sdhc(); 536 novena_spl_setup_iomux_spi(); 537 novena_spl_setup_iomux_uart(); 538 novena_spl_setup_iomux_video(); 539 540 /* UART clocks enabled and gd valid - init serial console */ 541 preloader_console_init(); 542 543 /* Start the DDR DRAM */ 544 mx6dq_dram_iocfg(64, &novena_ddr_ioregs, &novena_grp_ioregs); 545 mx6_dram_cfg(&novena_ddr_info, &novena_mmdc_calib, &elpida_4gib_1600); 546 547 /* Clear the BSS. */ 548 memset(__bss_start, 0, __bss_end - __bss_start); 549 550 /* load/boot image from boot device */ 551 board_init_r(NULL, 0); 552 } 553 554 void reset_cpu(ulong addr) 555 { 556 } 557