1 /* 2 * (C) Copyright 2009 3 * Marvell Semiconductor <www.marvell.com> 4 * Prafulla Wadaskar <prafulla@marvell.com> 5 * 6 * (C) Copyright 2009 7 * Stefan Roese, DENX Software Engineering, sr@denx.de. 8 * 9 * (C) Copyright 2010 10 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15 #include <common.h> 16 #include <i2c.h> 17 #include <nand.h> 18 #include <netdev.h> 19 #include <miiphy.h> 20 #include <spi.h> 21 #include <asm/io.h> 22 #include <asm/arch/cpu.h> 23 #include <asm/arch/kirkwood.h> 24 #include <asm/arch/mpp.h> 25 26 #include "../common/common.h" 27 28 DECLARE_GLOBAL_DATA_PTR; 29 30 /* 31 * BOCO FPGA definitions 32 */ 33 #define BOCO 0x10 34 #define REG_CTRL_H 0x02 35 #define MASK_WRL_UNITRUN 0x01 36 #define MASK_RBX_PGY_PRESENT 0x40 37 #define REG_IRQ_CIRQ2 0x2d 38 #define MASK_RBI_DEFECT_16 0x01 39 40 /* Multi-Purpose Pins Functionality configuration */ 41 static const u32 kwmpp_config[] = { 42 MPP0_NF_IO2, 43 MPP1_NF_IO3, 44 MPP2_NF_IO4, 45 MPP3_NF_IO5, 46 MPP4_NF_IO6, 47 MPP5_NF_IO7, 48 MPP6_SYSRST_OUTn, 49 MPP7_PEX_RST_OUTn, 50 #if defined(CONFIG_SYS_I2C_SOFT) 51 MPP8_GPIO, /* SDA */ 52 MPP9_GPIO, /* SCL */ 53 #endif 54 #if defined(CONFIG_HARD_I2C) 55 MPP8_TW_SDA, 56 MPP9_TW_SCK, 57 #endif 58 MPP10_UART0_TXD, 59 MPP11_UART0_RXD, 60 MPP12_GPO, /* Reserved */ 61 MPP13_UART1_TXD, 62 MPP14_UART1_RXD, 63 MPP15_GPIO, /* Not used */ 64 MPP16_GPIO, /* Not used */ 65 MPP17_GPIO, /* Reserved */ 66 MPP18_NF_IO0, 67 MPP19_NF_IO1, 68 MPP20_GPIO, 69 MPP21_GPIO, 70 MPP22_GPIO, 71 MPP23_GPIO, 72 MPP24_GPIO, 73 MPP25_GPIO, 74 MPP26_GPIO, 75 MPP27_GPIO, 76 MPP28_GPIO, 77 MPP29_GPIO, 78 MPP30_GPIO, 79 MPP31_GPIO, 80 MPP32_GPIO, 81 MPP33_GPIO, 82 MPP34_GPIO, /* CDL1 (input) */ 83 MPP35_GPIO, /* CDL2 (input) */ 84 MPP36_GPIO, /* MAIN_IRQ (input) */ 85 MPP37_GPIO, /* BOARD_LED */ 86 MPP38_GPIO, /* Piggy3 LED[1] */ 87 MPP39_GPIO, /* Piggy3 LED[2] */ 88 MPP40_GPIO, /* Piggy3 LED[3] */ 89 MPP41_GPIO, /* Piggy3 LED[4] */ 90 MPP42_GPIO, /* Piggy3 LED[5] */ 91 MPP43_GPIO, /* Piggy3 LED[6] */ 92 MPP44_GPIO, /* Piggy3 LED[7], BIST_EN_L */ 93 MPP45_GPIO, /* Piggy3 LED[8] */ 94 MPP46_GPIO, /* Reserved */ 95 MPP47_GPIO, /* Reserved */ 96 MPP48_GPIO, /* Reserved */ 97 MPP49_GPIO, /* SW_INTOUTn */ 98 0 99 }; 100 101 #if defined(CONFIG_KM_MGCOGE3UN) 102 /* 103 * Wait for startup OK from mgcoge3ne 104 */ 105 int startup_allowed(void) 106 { 107 unsigned char buf; 108 109 /* 110 * Read CIRQ16 bit (bit 0) 111 */ 112 if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0) 113 printf("%s: Error reading Boco\n", __func__); 114 else 115 if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16) 116 return 1; 117 return 0; 118 } 119 #endif 120 121 #if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352)) 122 /* 123 * All boards with PIGGY4 connected via a simple switch have ethernet always 124 * present. 125 */ 126 int ethernet_present(void) 127 { 128 return 1; 129 } 130 #else 131 int ethernet_present(void) 132 { 133 uchar buf; 134 int ret = 0; 135 136 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { 137 printf("%s: Error reading Boco\n", __func__); 138 return -1; 139 } 140 if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT) 141 ret = 1; 142 143 return ret; 144 } 145 #endif 146 147 static int initialize_unit_leds(void) 148 { 149 /* 150 * Init the unit LEDs per default they all are 151 * ok apart from bootstat 152 */ 153 uchar buf; 154 155 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { 156 printf("%s: Error reading Boco\n", __func__); 157 return -1; 158 } 159 buf |= MASK_WRL_UNITRUN; 160 if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { 161 printf("%s: Error writing Boco\n", __func__); 162 return -1; 163 } 164 return 0; 165 } 166 167 static void set_bootcount_addr(void) 168 { 169 uchar buf[32]; 170 unsigned int bootcountaddr; 171 bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR; 172 sprintf((char *)buf, "0x%x", bootcountaddr); 173 setenv("bootcountaddr", (char *)buf); 174 } 175 176 int misc_init_r(void) 177 { 178 #if defined(CONFIG_KM_MGCOGE3UN) 179 char *wait_for_ne; 180 wait_for_ne = getenv("waitforne"); 181 if (wait_for_ne != NULL) { 182 if (strcmp(wait_for_ne, "true") == 0) { 183 int cnt = 0; 184 int abort = 0; 185 puts("NE go: "); 186 while (startup_allowed() == 0) { 187 if (tstc()) { 188 (void) getc(); /* consume input */ 189 abort = 1; 190 break; 191 } 192 udelay(200000); 193 cnt++; 194 if (cnt == 5) 195 puts("wait\b\b\b\b"); 196 if (cnt == 10) { 197 cnt = 0; 198 puts(" \b\b\b\b"); 199 } 200 } 201 if (abort == 1) 202 printf("\nAbort waiting for ne\n"); 203 else 204 puts("OK\n"); 205 } 206 } 207 #endif 208 209 initialize_unit_leds(); 210 set_km_env(); 211 set_bootcount_addr(); 212 return 0; 213 } 214 215 int board_early_init_f(void) 216 { 217 #if defined(CONFIG_SYS_I2C_SOFT) 218 u32 tmp; 219 220 /* set the 2 bitbang i2c pins as output gpios */ 221 tmp = readl(KW_GPIO0_BASE + 4); 222 writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , KW_GPIO0_BASE + 4); 223 #endif 224 /* adjust SDRAM size for bank 0 */ 225 kw_sdram_size_adjust(0); 226 kirkwood_mpp_conf(kwmpp_config, NULL); 227 return 0; 228 } 229 230 int board_init(void) 231 { 232 /* address of boot parameters */ 233 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; 234 235 /* 236 * The KM_FLASH_GPIO_PIN switches between using a 237 * NAND or a SPI FLASH. Set this pin on start 238 * to NAND mode. 239 */ 240 kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1); 241 kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1); 242 243 #if defined(CONFIG_SYS_I2C_SOFT) 244 /* 245 * Reinit the GPIO for I2C Bitbang driver so that the now 246 * available gpio framework is consistent. The calls to 247 * direction output in are not necessary, they are already done in 248 * board_early_init_f 249 */ 250 kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1); 251 kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1); 252 #endif 253 254 #if defined(CONFIG_SYS_EEPROM_WREN) 255 kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38); 256 kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1); 257 #endif 258 259 #if defined(CONFIG_KM_FPGA_CONFIG) 260 trigger_fpga_config(); 261 #endif 262 263 return 0; 264 } 265 266 int board_late_init(void) 267 { 268 #if defined(CONFIG_KMCOGE5UN) 269 /* I/O pin to erase flash RGPP09 = MPP43 */ 270 #define KM_FLASH_ERASE_ENABLE 43 271 u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE); 272 273 /* if pin 1 do full erase */ 274 if (dip_switch != 0) { 275 /* start bootloader */ 276 puts("DIP: Enabled\n"); 277 setenv("actual_bank", "0"); 278 } 279 #endif 280 281 #if defined(CONFIG_KM_FPGA_CONFIG) 282 wait_for_fpga_config(); 283 fpga_reset(); 284 toggle_eeprom_spi_bus(); 285 #endif 286 return 0; 287 } 288 289 int board_spi_claim_bus(struct spi_slave *slave) 290 { 291 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0); 292 293 return 0; 294 } 295 296 void board_spi_release_bus(struct spi_slave *slave) 297 { 298 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1); 299 } 300 301 #if (defined(CONFIG_KM_PIGGY4_88E6061)) 302 303 #define PHY_LED_SEL_REG 0x18 304 #define PHY_LED0_LINK (0x5) 305 #define PHY_LED1_ACT (0x8<<4) 306 #define PHY_LED2_INT (0xe<<8) 307 #define PHY_SPEC_CTRL_REG 0x1c 308 #define PHY_RGMII_CLK_STABLE (0x1<<10) 309 #define PHY_CLSA (0x1<<1) 310 311 /* Configure and enable MV88E3018 PHY */ 312 void reset_phy(void) 313 { 314 char *name = "egiga0"; 315 unsigned short reg; 316 317 if (miiphy_set_current_dev(name)) 318 return; 319 320 /* RGMII clk transition on data stable */ 321 if (!miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®)) 322 printf("Error reading PHY spec ctrl reg\n"); 323 if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, 324 reg | PHY_RGMII_CLK_STABLE | PHY_CLSA)) 325 printf("Error writing PHY spec ctrl reg\n"); 326 327 /* leds setup */ 328 if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG, 329 PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT)) 330 printf("Error writing PHY LED reg\n"); 331 332 /* reset the phy */ 333 miiphy_reset(name, CONFIG_PHY_BASE_ADR); 334 } 335 #elif defined(CONFIG_KM_PIGGY4_88E6352) 336 337 #include <mv88e6352.h> 338 339 #if defined(CONFIG_KM_NUSA) 340 struct mv88e_sw_reg extsw_conf[] = { 341 /* 342 * port 0, PIGGY4, autoneg 343 * first the fix for the 1000Mbits Autoneg, this is from 344 * a Marvell errata, the regs are undocumented 345 */ 346 { PHY(0), PHY_PAGE, AN1000FIX_PAGE }, 347 { PHY(0), PHY_STATUS, AN1000FIX }, 348 { PHY(0), PHY_PAGE, 0 }, 349 /* now the real port and phy configuration */ 350 { PORT(0), PORT_PHY, NO_SPEED_FOR }, 351 { PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, 352 { PHY(0), PHY_1000_CTRL, NO_ADV }, 353 { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN }, 354 { PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST | 355 FULL_DUPLEX }, 356 /* port 1, unused */ 357 { PORT(1), PORT_CTRL, PORT_DIS }, 358 { PHY(1), PHY_CTRL, PHY_PWR_DOWN }, 359 { PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, 360 /* port 2, unused */ 361 { PORT(2), PORT_CTRL, PORT_DIS }, 362 { PHY(2), PHY_CTRL, PHY_PWR_DOWN }, 363 { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, 364 /* port 3, unused */ 365 { PORT(3), PORT_CTRL, PORT_DIS }, 366 { PHY(3), PHY_CTRL, PHY_PWR_DOWN }, 367 { PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, 368 /* port 4, ICNEV, SerDes, SGMII */ 369 { PORT(4), PORT_STATUS, NO_PHY_DETECT }, 370 { PORT(4), PORT_PHY, SPEED_1000_FOR }, 371 { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, 372 { PHY(4), PHY_CTRL, PHY_PWR_DOWN }, 373 { PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, 374 /* port 5, CPU_RGMII */ 375 { PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN | 376 FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX | 377 FULL_DPX_FOR | SPEED_1000_FOR }, 378 { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, 379 /* port 6, unused, this port has no phy */ 380 { PORT(6), PORT_CTRL, PORT_DIS }, 381 }; 382 #else 383 struct mv88e_sw_reg extsw_conf[] = {}; 384 #endif 385 386 void reset_phy(void) 387 { 388 #if defined(CONFIG_KM_MVEXTSW_ADDR) 389 char *name = "egiga0"; 390 391 if (miiphy_set_current_dev(name)) 392 return; 393 394 mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf, 395 ARRAY_SIZE(extsw_conf)); 396 mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR); 397 #endif 398 } 399 400 #else 401 /* Configure and enable MV88E1118 PHY on the piggy*/ 402 void reset_phy(void) 403 { 404 char *name = "egiga0"; 405 406 if (miiphy_set_current_dev(name)) 407 return; 408 409 /* reset the phy */ 410 miiphy_reset(name, CONFIG_PHY_BASE_ADR); 411 } 412 #endif 413 414 415 #if defined(CONFIG_HUSH_INIT_VAR) 416 int hush_init_var(void) 417 { 418 ivm_read_eeprom(); 419 return 0; 420 } 421 #endif 422 423 #if defined(CONFIG_SYS_I2C_SOFT) 424 void set_sda(int state) 425 { 426 I2C_ACTIVE; 427 I2C_SDA(state); 428 } 429 430 void set_scl(int state) 431 { 432 I2C_SCL(state); 433 } 434 435 int get_sda(void) 436 { 437 I2C_TRISTATE; 438 return I2C_READ; 439 } 440 441 int get_scl(void) 442 { 443 return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0; 444 } 445 #endif 446 447 #if defined(CONFIG_POST) 448 449 #define KM_POST_EN_L 44 450 #define POST_WORD_OFF 8 451 452 int post_hotkeys_pressed(void) 453 { 454 #if defined(CONFIG_KM_COGE5UN) 455 return kw_gpio_get_value(KM_POST_EN_L); 456 #else 457 return !kw_gpio_get_value(KM_POST_EN_L); 458 #endif 459 } 460 461 ulong post_word_load(void) 462 { 463 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF); 464 return in_le32(addr); 465 466 } 467 void post_word_store(ulong value) 468 { 469 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF); 470 out_le32(addr, value); 471 } 472 473 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 474 { 475 *vstart = CONFIG_SYS_SDRAM_BASE; 476 477 /* we go up to relocation plus a 1 MB margin */ 478 *size = CONFIG_SYS_TEXT_BASE - (1<<20); 479 480 return 0; 481 } 482 #endif 483 484 #if defined(CONFIG_SYS_EEPROM_WREN) 485 int eeprom_write_enable(unsigned dev_addr, int state) 486 { 487 kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state); 488 489 return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP); 490 } 491 #endif 492