xref: /rk3399_rockchip-uboot/board/imx31_phycore/lowlevel_init.S (revision eca3aeb352c964bdb28b8e191d6326370245e03f)
1/*
2 *
3 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <asm/arch/imx-regs.h>
25
26.macro REG reg, val
27	ldr r2, =\reg
28	ldr r3, =\val
29	str r3, [r2]
30.endm
31
32.macro REG8 reg, val
33	ldr r2, =\reg
34	ldr r3, =\val
35	strb r3, [r2]
36.endm
37
38.macro DELAY loops
39	ldr r2, =\loops
401:
41	subs	r2, r2, #1
42	nop
43	bcs 1b
44.endm
45
46.globl lowlevel_init
47lowlevel_init:
48
49	REG	IPU_CONF, IPU_CONF_DI_EN
50	REG	CCM_CCMR, 0x074B0BF5
51
52	DELAY 0x40000
53
54	REG	CCM_CCMR, 0x074B0BF5 | CCMR_MPE
55	REG	CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
56
57	REG	CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)
58
59	REG	CCM_MPCTL, PLL_PD(0) | PLL_MFD(0xe) | PLL_MFI(9) | PLL_MFN(0xd)
60
61	REG	CCM_SPCTL, PLL_PD(1) | PLL_MFD(0x43) | PLL_MFI(12) | PLL_MFN(1)
62
63	REG	0x43FAC26C, 0 /* SDCLK */
64	REG	0x43FAC270, 0 /* CAS */
65	REG	0x43FAC274, 0 /* RAS */
66	REG	0x43FAC27C, 0x1000 /* CS2 (CSD0) */
67	REG	0x43FAC284, 0 /* DQM3 */
68	REG	0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
69	REG	0x43FAC28C, 0
70	REG	0x43FAC290, 0
71	REG	0x43FAC294, 0
72	REG	0x43FAC298, 0
73	REG	0x43FAC29C, 0
74	REG	0x43FAC2A0, 0
75	REG	0x43FAC2A4, 0
76	REG	0x43FAC2A8, 0
77	REG	0x43FAC2AC, 0
78	REG	0x43FAC2B0, 0
79	REG	0x43FAC2B4, 0
80	REG	0x43FAC2B8, 0
81	REG	0x43FAC2BC, 0
82	REG	0x43FAC2C0, 0
83	REG	0x43FAC2C4, 0
84	REG	0x43FAC2C8, 0
85	REG	0x43FAC2CC, 0
86	REG	0x43FAC2D0, 0
87	REG	0x43FAC2D4, 0
88	REG	0x43FAC2D8, 0
89	REG	0x43FAC2DC, 0
90	REG	0xB8001010, 0x00000004
91	REG	0xB8001004, 0x006ac73a
92	REG	0xB8001000, 0x92100000
93	REG	0x80000f00, 0x12344321
94	REG	0xB8001000, 0xa2100000
95	REG	0x80000000, 0x12344321
96	REG	0x80000000, 0x12344321
97	REG	0xB8001000, 0xb2100000
98	REG8	0x80000033, 0xda
99	REG8	0x81000000, 0xff
100	REG	0xB8001000, 0x82226080
101	REG	0x80000000, 0xDEADBEEF
102	REG	0xB8001010, 0x0000000c
103
104	mov	pc, lr
105