1 /* 2 * 3 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 9 #include <common.h> 10 #include <s6e63d6.h> 11 #include <netdev.h> 12 #include <asm/arch/clock.h> 13 #include <asm/arch/imx-regs.h> 14 #include <asm/mach-types.h> 15 #include <asm/arch/sys_proto.h> 16 17 DECLARE_GLOBAL_DATA_PTR; 18 19 int dram_init(void) 20 { 21 /* dram_init must store complete ramsize in gd->ram_size */ 22 gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, 23 PHYS_SDRAM_1_SIZE); 24 return 0; 25 } 26 27 int board_init(void) 28 { 29 30 gd->bd->bi_arch_number = MACH_TYPE_PCM037; /* board id for linux */ 31 gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */ 32 33 return 0; 34 } 35 36 int board_early_init_f(void) 37 { 38 /* CS0: Nor Flash */ 39 static const struct mxc_weimcs cs0 = { 40 /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ 41 CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3), 42 /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ 43 CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1), 44 /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ 45 CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0) 46 }; 47 48 /* CS1: Network Controller */ 49 static const struct mxc_weimcs cs1 = { 50 /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ 51 CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 31, 0, 0, 6), 52 /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ 53 CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1), 54 /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ 55 CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0) 56 }; 57 58 /* CS4: SRAM */ 59 static const struct mxc_weimcs cs4 = { 60 /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ 61 CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3), 62 /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ 63 CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1), 64 /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ 65 CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0) 66 }; 67 68 mxc_setup_weimcs(0, &cs0); 69 mxc_setup_weimcs(1, &cs1); 70 mxc_setup_weimcs(4, &cs4); 71 72 /* setup pins for UART1 */ 73 mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); 74 mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX); 75 mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); 76 mx31_gpio_mux(MUX_CTS1__UART1_CTS_B); 77 78 /* setup pins for I2C2 (for EEPROM, RTC) */ 79 mx31_gpio_mux(MUX_CSPI2_MOSI__I2C2_SCL); 80 mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SDA); 81 82 return 0; 83 } 84 85 #ifdef CONFIG_BOARD_LATE_INIT 86 int board_late_init(void) 87 { 88 #ifdef CONFIG_S6E63D6 89 struct s6e63d6 data = { 90 /* 91 * See comment in mxc_spi.c::decode_cs() for .cs field format. 92 * We use GPIO 57 as a chipselect for the S6E63D6 and chipselect 93 * 2 of the SPI controller #1, since it is unused. 94 */ 95 .cs = 2 | (57 << 8), 96 .bus = 0, 97 .id = 0, 98 }; 99 int ret; 100 101 /* SPI1 */ 102 mx31_gpio_mux(MUX_CSPI1_SCLK__CSPI1_CLK); 103 mx31_gpio_mux(MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B); 104 mx31_gpio_mux(MUX_CSPI1_MOSI__CSPI1_MOSI); 105 mx31_gpio_mux(MUX_CSPI1_MISO__CSPI1_MISO); 106 mx31_gpio_mux(MUX_CSPI1_SS0__CSPI1_SS0_B); 107 mx31_gpio_mux(MUX_CSPI1_SS1__CSPI1_SS1_B); 108 mx31_gpio_mux(MUX_CSPI1_SS2__CSPI1_SS2_B); 109 110 /* start SPI1 clock */ 111 __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 2); 112 113 /* GPIO 57 */ 114 /* sw_mux_ctl_key_col4_key_col5_key_col6_key_col7 */ 115 mx31_gpio_mux(IOMUX_MODE(0x63, MUX_CTL_GPIO)); 116 117 /* SPI1 CS2 is free */ 118 ret = s6e63d6_init(&data); 119 if (ret) 120 return ret; 121 122 /* 123 * This is a "magic" sequence to initialise a C0240QGLA / C0283QGLC 124 * OLED display connected to a S6E63D6 SPI display controller in the 125 * 18 bit RGB mode 126 */ 127 s6e63d6_index(&data, 2); 128 s6e63d6_param(&data, 0x0182); 129 s6e63d6_index(&data, 3); 130 s6e63d6_param(&data, 0x8130); 131 s6e63d6_index(&data, 0x10); 132 s6e63d6_param(&data, 0x0000); 133 s6e63d6_index(&data, 5); 134 s6e63d6_param(&data, 0x0001); 135 s6e63d6_index(&data, 0x22); 136 #endif 137 return 0; 138 } 139 #endif 140 141 int checkboard (void) 142 { 143 printf("Board: Phytec phyCore i.MX31\n"); 144 return 0; 145 } 146 147 int board_eth_init(bd_t *bis) 148 { 149 int rc = 0; 150 #ifdef CONFIG_SMC911X 151 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); 152 #endif 153 return rc; 154 } 155