1*ebf2b9e3SZubair Lutfullah Kakakhel /* 2*ebf2b9e3SZubair Lutfullah Kakakhel * Imagination Technologies MIPSfpga platform code 3*ebf2b9e3SZubair Lutfullah Kakakhel * 4*ebf2b9e3SZubair Lutfullah Kakakhel * Copyright (C) 2016, Imagination Technologies Ltd. 5*ebf2b9e3SZubair Lutfullah Kakakhel * 6*ebf2b9e3SZubair Lutfullah Kakakhel * Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> 7*ebf2b9e3SZubair Lutfullah Kakakhel * 8*ebf2b9e3SZubair Lutfullah Kakakhel * SPDX-License-Identifier: GPL-2.0+ 9*ebf2b9e3SZubair Lutfullah Kakakhel * 10*ebf2b9e3SZubair Lutfullah Kakakhel */ 11*ebf2b9e3SZubair Lutfullah Kakakhel 12*ebf2b9e3SZubair Lutfullah Kakakhel #include <common.h> 13*ebf2b9e3SZubair Lutfullah Kakakhel 14*ebf2b9e3SZubair Lutfullah Kakakhel /* initialize the DDR Controller and PHY */ 15*ebf2b9e3SZubair Lutfullah Kakakhel phys_size_t initdram(int board_type) 16*ebf2b9e3SZubair Lutfullah Kakakhel { 17*ebf2b9e3SZubair Lutfullah Kakakhel /* MIG IP block is smart and doesn't need SW 18*ebf2b9e3SZubair Lutfullah Kakakhel * to do any init */ 19*ebf2b9e3SZubair Lutfullah Kakakhel return CONFIG_SYS_SDRAM_SIZE; /* in bytes */ 20*ebf2b9e3SZubair Lutfullah Kakakhel } 21