1ebf2b9e3SZubair Lutfullah Kakakhel /* 2ebf2b9e3SZubair Lutfullah Kakakhel * Imagination Technologies MIPSfpga platform code 3ebf2b9e3SZubair Lutfullah Kakakhel * 4ebf2b9e3SZubair Lutfullah Kakakhel * Copyright (C) 2016, Imagination Technologies Ltd. 5ebf2b9e3SZubair Lutfullah Kakakhel * 6ebf2b9e3SZubair Lutfullah Kakakhel * Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> 7ebf2b9e3SZubair Lutfullah Kakakhel * 8ebf2b9e3SZubair Lutfullah Kakakhel * SPDX-License-Identifier: GPL-2.0+ 9ebf2b9e3SZubair Lutfullah Kakakhel * 10ebf2b9e3SZubair Lutfullah Kakakhel */ 11ebf2b9e3SZubair Lutfullah Kakakhel 12ebf2b9e3SZubair Lutfullah Kakakhel #include <common.h> 13ebf2b9e3SZubair Lutfullah Kakakhel 14088454cdSSimon Glass DECLARE_GLOBAL_DATA_PTR; 15088454cdSSimon Glass 16ebf2b9e3SZubair Lutfullah Kakakhel /* initialize the DDR Controller and PHY */ dram_init(void)17*f1683aa7SSimon Glassint dram_init(void) 18ebf2b9e3SZubair Lutfullah Kakakhel { 19ebf2b9e3SZubair Lutfullah Kakakhel /* MIG IP block is smart and doesn't need SW 20ebf2b9e3SZubair Lutfullah Kakakhel * to do any init */ 21088454cdSSimon Glass gd->ram_size = CONFIG_SYS_SDRAM_SIZE; /* in bytes */ 22088454cdSSimon Glass 23088454cdSSimon Glass return 0; 24ebf2b9e3SZubair Lutfullah Kakakhel } 25