1 /* 2 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org> 3 * Copyright (C) 2013 Imagination Technologies 4 * 5 * SPDX-License-Identifier: GPL-2.0 6 */ 7 8 #include <common.h> 9 #include <netdev.h> 10 #include <pci_gt64120.h> 11 #include <pci_msc01.h> 12 #include <serial.h> 13 14 #include <asm/addrspace.h> 15 #include <asm/io.h> 16 #include <asm/malta.h> 17 18 #include "superio.h" 19 20 enum core_card { 21 CORE_UNKNOWN, 22 CORE_LV, 23 CORE_FPGA6, 24 }; 25 26 enum sys_con { 27 SYSCON_UNKNOWN, 28 SYSCON_GT64120, 29 SYSCON_MSC01, 30 }; 31 32 static void malta_lcd_puts(const char *str) 33 { 34 int i; 35 void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0); 36 37 /* print up to 8 characters of the string */ 38 for (i = 0; i < min(strlen(str), 8); i++) { 39 __raw_writel(str[i], reg); 40 reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0; 41 } 42 43 /* fill the rest of the display with spaces */ 44 for (; i < 8; i++) { 45 __raw_writel(' ', reg); 46 reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0; 47 } 48 } 49 50 static enum core_card malta_core_card(void) 51 { 52 u32 corid, rev; 53 54 rev = __raw_readl(CKSEG1ADDR(MALTA_REVISION)); 55 corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF; 56 57 switch (corid) { 58 case MALTA_REVISION_CORID_CORE_LV: 59 return CORE_LV; 60 61 case MALTA_REVISION_CORID_CORE_FPGA6: 62 return CORE_FPGA6; 63 64 default: 65 return CORE_UNKNOWN; 66 } 67 } 68 69 static enum sys_con malta_sys_con(void) 70 { 71 switch (malta_core_card()) { 72 case CORE_LV: 73 return SYSCON_GT64120; 74 75 case CORE_FPGA6: 76 return SYSCON_MSC01; 77 78 default: 79 return SYSCON_UNKNOWN; 80 } 81 } 82 83 phys_size_t initdram(int board_type) 84 { 85 return CONFIG_SYS_MEM_SIZE; 86 } 87 88 int checkboard(void) 89 { 90 enum core_card core; 91 92 malta_lcd_puts("U-boot"); 93 puts("Board: MIPS Malta"); 94 95 core = malta_core_card(); 96 switch (core) { 97 case CORE_LV: 98 puts(" CoreLV"); 99 break; 100 101 case CORE_FPGA6: 102 puts(" CoreFPGA6"); 103 break; 104 105 default: 106 puts(" CoreUnknown"); 107 } 108 109 putc('\n'); 110 return 0; 111 } 112 113 int board_eth_init(bd_t *bis) 114 { 115 return pci_eth_init(bis); 116 } 117 118 void _machine_restart(void) 119 { 120 void __iomem *reset_base; 121 122 reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE); 123 __raw_writel(GORESET, reset_base); 124 } 125 126 int board_early_init_f(void) 127 { 128 void *io_base; 129 130 /* choose correct PCI I/O base */ 131 switch (malta_sys_con()) { 132 case SYSCON_GT64120: 133 io_base = (void *)CKSEG1ADDR(MALTA_GT_PCIIO_BASE); 134 break; 135 136 case SYSCON_MSC01: 137 io_base = (void *)CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE); 138 break; 139 140 default: 141 return -1; 142 } 143 144 /* setup FDC37M817 super I/O controller */ 145 malta_superio_init(io_base); 146 147 return 0; 148 } 149 150 struct serial_device *default_serial_console(void) 151 { 152 switch (malta_sys_con()) { 153 case SYSCON_GT64120: 154 return &eserial1_device; 155 156 default: 157 case SYSCON_MSC01: 158 return &eserial2_device; 159 } 160 } 161 162 void pci_init_board(void) 163 { 164 switch (malta_sys_con()) { 165 case SYSCON_GT64120: 166 set_io_port_base(CKSEG1ADDR(MALTA_GT_PCIIO_BASE)); 167 168 gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE), 169 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE, 170 0x10000000, 0x10000000, 128 * 1024 * 1024, 171 0x00000000, 0x00000000, 0x20000); 172 break; 173 174 default: 175 case SYSCON_MSC01: 176 set_io_port_base(CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE)); 177 178 msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE), 179 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE, 180 MALTA_MSC01_PCIMEM_MAP, 181 CKSEG1ADDR(MALTA_MSC01_PCIMEM_BASE), 182 MALTA_MSC01_PCIMEM_SIZE, MALTA_MSC01_PCIIO_MAP, 183 0x00000000, MALTA_MSC01_PCIIO_SIZE); 184 break; 185 } 186 } 187