1*7a9d109bSPaul Burton/* 2*7a9d109bSPaul Burton * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org> 3*7a9d109bSPaul Burton * 4*7a9d109bSPaul Burton * SPDX-License-Identifier: GPL-2.0 5*7a9d109bSPaul Burton */ 6*7a9d109bSPaul Burton 7*7a9d109bSPaul Burton#include <config.h> 8*7a9d109bSPaul Burton#include <gt64120.h> 9*7a9d109bSPaul Burton 10*7a9d109bSPaul Burton#include <asm/addrspace.h> 11*7a9d109bSPaul Burton#include <asm/regdef.h> 12*7a9d109bSPaul Burton#include <asm/malta.h> 13*7a9d109bSPaul Burton 14*7a9d109bSPaul Burton#ifdef CONFIG_SYS_BIG_ENDIAN 15*7a9d109bSPaul Burton#define CPU_TO_GT32(_x) ((_x)) 16*7a9d109bSPaul Burton#else 17*7a9d109bSPaul Burton#define CPU_TO_GT32(_x) ( \ 18*7a9d109bSPaul Burton (((_x) & 0xff) << 24) | (((_x) & 0xff00) << 8) | \ 19*7a9d109bSPaul Burton (((_x) & 0xff0000) >> 8) | (((_x) & 0xff000000) >> 24)) 20*7a9d109bSPaul Burton#endif 21*7a9d109bSPaul Burton 22*7a9d109bSPaul Burton .text 23*7a9d109bSPaul Burton .set noreorder 24*7a9d109bSPaul Burton .set mips32 25*7a9d109bSPaul Burton 26*7a9d109bSPaul Burton .globl lowlevel_init 27*7a9d109bSPaul Burtonlowlevel_init: 28*7a9d109bSPaul Burton 29*7a9d109bSPaul Burton /* 30*7a9d109bSPaul Burton * Load BAR registers of GT64120 as done by YAMON 31*7a9d109bSPaul Burton * 32*7a9d109bSPaul Burton * based on a patch sent by Antony Pavlov <antonynpavlov@gmail.com> 33*7a9d109bSPaul Burton * to the barebox mailing list. 34*7a9d109bSPaul Burton * The subject of the original patch: 35*7a9d109bSPaul Burton * 'MIPS: qemu-malta: add YAMON-style GT64120 memory map' 36*7a9d109bSPaul Burton * URL: 37*7a9d109bSPaul Burton * http://www.mail-archive.com/barebox@lists.infradead.org/msg06128.html 38*7a9d109bSPaul Burton * 39*7a9d109bSPaul Burton * based on write_bootloader() in qemu.git/hw/mips_malta.c 40*7a9d109bSPaul Burton * see GT64120 manual and qemu.git/hw/gt64xxx.c for details 41*7a9d109bSPaul Burton */ 42*7a9d109bSPaul Burton 43*7a9d109bSPaul Burton /* move GT64120 registers from 0x14000000 to 0x1be00000 */ 44*7a9d109bSPaul Burton li t1, KSEG1ADDR(GT_DEF_BASE) 45*7a9d109bSPaul Burton li t0, CPU_TO_GT32(0xdf000000) 46*7a9d109bSPaul Burton sw t0, GT_ISD_OFS(t1) 47*7a9d109bSPaul Burton 48*7a9d109bSPaul Burton /* setup MEM-to-PCI0 mapping */ 49*7a9d109bSPaul Burton li t1, KSEG1ADDR(MALTA_GT_BASE) 50*7a9d109bSPaul Burton 51*7a9d109bSPaul Burton /* setup PCI0 io window to 0x18000000-0x181fffff */ 52*7a9d109bSPaul Burton li t0, CPU_TO_GT32(0xc0000000) 53*7a9d109bSPaul Burton sw t0, GT_PCI0IOLD_OFS(t1) 54*7a9d109bSPaul Burton li t0, CPU_TO_GT32(0x40000000) 55*7a9d109bSPaul Burton sw t0, GT_PCI0IOHD_OFS(t1) 56*7a9d109bSPaul Burton 57*7a9d109bSPaul Burton /* setup PCI0 mem windows */ 58*7a9d109bSPaul Burton li t0, CPU_TO_GT32(0x80000000) 59*7a9d109bSPaul Burton sw t0, GT_PCI0M0LD_OFS(t1) 60*7a9d109bSPaul Burton li t0, CPU_TO_GT32(0x3f000000) 61*7a9d109bSPaul Burton sw t0, GT_PCI0M0HD_OFS(t1) 62*7a9d109bSPaul Burton 63*7a9d109bSPaul Burton li t0, CPU_TO_GT32(0xc1000000) 64*7a9d109bSPaul Burton sw t0, GT_PCI0M1LD_OFS(t1) 65*7a9d109bSPaul Burton li t0, CPU_TO_GT32(0x5e000000) 66*7a9d109bSPaul Burton sw t0, GT_PCI0M1HD_OFS(t1) 67*7a9d109bSPaul Burton 68*7a9d109bSPaul Burton jr ra 69*7a9d109bSPaul Burton nop 70