xref: /rk3399_rockchip-uboot/board/gdsys/p1022/ddr.c (revision 5b8031ccb4ed6e84457d883198d77efc307085dc)
1b9944a77SDirk Eibach /*
2b9944a77SDirk Eibach  * Copyright 2010 Freescale Semiconductor, Inc.
3b9944a77SDirk Eibach  * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
4b9944a77SDirk Eibach  *          Timur Tabi <timur@freescale.com>
5b9944a77SDirk Eibach  *
6*5b8031ccSTom Rini  * SPDX-License-Identifier:	GPL-2.0+
7b9944a77SDirk Eibach  */
8b9944a77SDirk Eibach 
9b9944a77SDirk Eibach #include <common.h>
10b9944a77SDirk Eibach #include <i2c.h>
11b9944a77SDirk Eibach 
125614e71bSYork Sun #include <fsl_ddr_sdram.h>
135614e71bSYork Sun #include <fsl_ddr_dimm_params.h>
14b9944a77SDirk Eibach 
fsl_ddr_board_options(memctl_options_t * popts,dimm_params_t * pdimm,unsigned int ctrl_num)15b9944a77SDirk Eibach void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
16b9944a77SDirk Eibach 			   unsigned int ctrl_num)
17b9944a77SDirk Eibach {
18b9944a77SDirk Eibach 	unsigned int i;
19b9944a77SDirk Eibach 
20b9944a77SDirk Eibach 	if (ctrl_num) {
21b9944a77SDirk Eibach 		printf("Wrong parameter for controller number %d", ctrl_num);
22b9944a77SDirk Eibach 		return;
23b9944a77SDirk Eibach 	}
24b9944a77SDirk Eibach 	if (!pdimm->n_ranks)
25b9944a77SDirk Eibach 		return;
26b9944a77SDirk Eibach 
27b9944a77SDirk Eibach 	/* set odt_rd_cfg and odt_wr_cfg. */
28b9944a77SDirk Eibach 	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
29b9944a77SDirk Eibach 		popts->cs_local_opts[i].odt_rd_cfg = 0;
30b9944a77SDirk Eibach 		popts->cs_local_opts[i].odt_wr_cfg = 1;
31b9944a77SDirk Eibach 	}
32b9944a77SDirk Eibach 
33b9944a77SDirk Eibach 	popts->clk_adjust = 5;
34b9944a77SDirk Eibach 	popts->cpo_override = 0x1f;
35b9944a77SDirk Eibach 	popts->write_data_delay = 2;
36b9944a77SDirk Eibach 	popts->half_strength_driver_enable = 1;
37b9944a77SDirk Eibach 
38b9944a77SDirk Eibach 	/* Per AN4039, enable ZQ calibration. */
39b9944a77SDirk Eibach 	popts->zq_en = 1;
40b9944a77SDirk Eibach }
41b9944a77SDirk Eibach 
42b9944a77SDirk Eibach #ifdef CONFIG_SPD_EEPROM
43b9944a77SDirk Eibach /*
44b9944a77SDirk Eibach  * we only have a "fake" SPD-EEPROM here, which has 16 bit addresses
45b9944a77SDirk Eibach  */
get_spd(generic_spd_eeprom_t * spd,u8 i2c_address)46b9944a77SDirk Eibach void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
47b9944a77SDirk Eibach {
48b9944a77SDirk Eibach 	int ret = i2c_read(i2c_address, 0, 2, (uchar *)spd,
49b9944a77SDirk Eibach 				sizeof(generic_spd_eeprom_t));
50b9944a77SDirk Eibach 
51b9944a77SDirk Eibach 	if (ret) {
52b9944a77SDirk Eibach 		if (i2c_address ==
53b9944a77SDirk Eibach #ifdef SPD_EEPROM_ADDRESS
54b9944a77SDirk Eibach 				SPD_EEPROM_ADDRESS
55b9944a77SDirk Eibach #elif defined(SPD_EEPROM_ADDRESS1)
56b9944a77SDirk Eibach 				SPD_EEPROM_ADDRESS1
57b9944a77SDirk Eibach #endif
58b9944a77SDirk Eibach 				) {
59b9944a77SDirk Eibach 			printf("DDR: failed to read SPD from address %u\n",
60b9944a77SDirk Eibach 			       i2c_address);
61b9944a77SDirk Eibach 		} else {
62b9944a77SDirk Eibach 			debug("DDR: failed to read SPD from address %u\n",
63b9944a77SDirk Eibach 			      i2c_address);
64b9944a77SDirk Eibach 		}
65b9944a77SDirk Eibach 		memset(spd, 0, sizeof(generic_spd_eeprom_t));
66b9944a77SDirk Eibach 	}
67b9944a77SDirk Eibach }
68b9944a77SDirk Eibach #endif
69