1 /* 2 * (C) Copyright 2010 3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <i2c.h> 10 #include <malloc.h> 11 12 #include <gdsys_fpga.h> 13 14 #define CH7301_I2C_ADDR 0x75 15 16 #define ICS8N3QV01_I2C_ADDR 0x6E 17 #define ICS8N3QV01_FREF 114285000 18 #define ICS8N3QV01_FREF_LL 114285000LL 19 #define ICS8N3QV01_F_DEFAULT_0 156250000LL 20 #define ICS8N3QV01_F_DEFAULT_1 125000000LL 21 #define ICS8N3QV01_F_DEFAULT_2 100000000LL 22 #define ICS8N3QV01_F_DEFAULT_3 25175000LL 23 24 #define SIL1178_MASTER_I2C_ADDRESS 0x38 25 #define SIL1178_SLAVE_I2C_ADDRESS 0x39 26 27 #define PIXCLK_640_480_60 25180000 28 29 #define BASE_WIDTH 32 30 #define BASE_HEIGHT 16 31 #define BUFSIZE (BASE_WIDTH * BASE_HEIGHT) 32 33 enum { 34 CH7301_CM = 0x1c, /* Clock Mode Register */ 35 CH7301_IC = 0x1d, /* Input Clock Register */ 36 CH7301_GPIO = 0x1e, /* GPIO Control Register */ 37 CH7301_IDF = 0x1f, /* Input Data Format Register */ 38 CH7301_CD = 0x20, /* Connection Detect Register */ 39 CH7301_DC = 0x21, /* DAC Control Register */ 40 CH7301_HPD = 0x23, /* Hot Plug Detection Register */ 41 CH7301_TCTL = 0x31, /* DVI Control Input Register */ 42 CH7301_TPCP = 0x33, /* DVI PLL Charge Pump Ctrl Register */ 43 CH7301_TPD = 0x34, /* DVI PLL Divide Register */ 44 CH7301_TPVT = 0x35, /* DVI PLL Supply Control Register */ 45 CH7301_TPF = 0x36, /* DVI PLL Filter Register */ 46 CH7301_TCT = 0x37, /* DVI Clock Test Register */ 47 CH7301_TSTP = 0x48, /* Test Pattern Register */ 48 CH7301_PM = 0x49, /* Power Management register */ 49 CH7301_VID = 0x4a, /* Version ID Register */ 50 CH7301_DID = 0x4b, /* Device ID Register */ 51 CH7301_DSP = 0x56, /* DVI Sync polarity Register */ 52 }; 53 54 unsigned int max_osd_screen = CONFIG_SYS_OSD_SCREENS - 1; 55 56 #ifdef CONFIG_SYS_CH7301 57 int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C; 58 #endif 59 60 #if defined(CONFIG_SYS_ICS8N3QV01) || defined(CONFIG_SYS_SIL1178) 61 static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data) 62 { 63 u16 val; 64 65 do { 66 FPGA_GET_REG(screen, extended_interrupt, &val); 67 } while (val & (1 << 12)); 68 69 FPGA_SET_REG(screen, i2c.write_mailbox_ext, reg | (data << 8)); 70 FPGA_SET_REG(screen, i2c.write_mailbox, 0xc400 | (slave << 1)); 71 } 72 73 static u8 fpga_iic_read(unsigned screen, u8 slave, u8 reg) 74 { 75 unsigned int ctr = 0; 76 u16 val; 77 78 do { 79 FPGA_GET_REG(screen, extended_interrupt, &val); 80 } while (val & (1 << 12)); 81 82 FPGA_SET_REG(screen, extended_interrupt, 1 << 14); 83 FPGA_SET_REG(screen, i2c.write_mailbox_ext, reg); 84 FPGA_SET_REG(screen, i2c.write_mailbox, 0xc000 | (slave << 1)); 85 86 FPGA_GET_REG(screen, extended_interrupt, &val); 87 while (!(val & (1 << 14))) { 88 udelay(100000); 89 if (ctr++ > 5) { 90 printf("iic receive timeout\n"); 91 break; 92 } 93 FPGA_GET_REG(screen, extended_interrupt, &val); 94 } 95 96 FPGA_GET_REG(screen, i2c.read_mailbox_ext, &val); 97 return val >> 8; 98 } 99 #endif 100 101 #ifdef CONFIG_SYS_MPC92469AC 102 static void mpc92469ac_calc_parameters(unsigned int fout, 103 unsigned int *post_div, unsigned int *feedback_div) 104 { 105 unsigned int n = *post_div; 106 unsigned int m = *feedback_div; 107 unsigned int a; 108 unsigned int b = 14745600 / 16; 109 110 if (fout < 50169600) 111 n = 8; 112 else if (fout < 100339199) 113 n = 4; 114 else if (fout < 200678399) 115 n = 2; 116 else 117 n = 1; 118 119 a = fout * n + (b / 2); /* add b/2 for proper rounding */ 120 121 m = a / b; 122 123 *post_div = n; 124 *feedback_div = m; 125 } 126 127 static void mpc92469ac_set(unsigned screen, unsigned int fout) 128 { 129 unsigned int n; 130 unsigned int m; 131 unsigned int bitval = 0; 132 mpc92469ac_calc_parameters(fout, &n, &m); 133 134 switch (n) { 135 case 1: 136 bitval = 0x00; 137 break; 138 case 2: 139 bitval = 0x01; 140 break; 141 case 4: 142 bitval = 0x02; 143 break; 144 case 8: 145 bitval = 0x03; 146 break; 147 } 148 149 FPGA_SET_REG(screen, mpc3w_control, (bitval << 9) | m); 150 } 151 #endif 152 153 #ifdef CONFIG_SYS_ICS8N3QV01 154 155 static unsigned int ics8n3qv01_get_fout_calc(unsigned screen, unsigned index) 156 { 157 unsigned long long n; 158 unsigned long long mint; 159 unsigned long long mfrac; 160 u8 reg_a, reg_b, reg_c, reg_d, reg_f; 161 unsigned long long fout_calc; 162 163 if (index > 3) 164 return 0; 165 166 reg_a = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0 + index); 167 reg_b = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 4 + index); 168 reg_c = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 8 + index); 169 reg_d = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 12 + index); 170 reg_f = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 20 + index); 171 172 mint = ((reg_a >> 1) & 0x1f) | (reg_f & 0x20); 173 mfrac = ((reg_a & 0x01) << 17) | (reg_b << 9) | (reg_c << 1) 174 | (reg_d >> 7); 175 n = reg_d & 0x7f; 176 177 fout_calc = (mint * ICS8N3QV01_FREF_LL 178 + mfrac * ICS8N3QV01_FREF_LL / 262144LL 179 + ICS8N3QV01_FREF_LL / 524288LL 180 + n / 2) 181 / n 182 * 1000000 183 / (1000000 - 100); 184 185 return fout_calc; 186 } 187 188 189 static void ics8n3qv01_calc_parameters(unsigned int fout, 190 unsigned int *_mint, unsigned int *_mfrac, 191 unsigned int *_n) 192 { 193 unsigned int n; 194 unsigned int foutiic; 195 unsigned int fvcoiic; 196 unsigned int mint; 197 unsigned long long mfrac; 198 199 n = (2215000000U + fout / 2) / fout; 200 if ((n & 1) && (n > 5)) 201 n -= 1; 202 203 foutiic = fout - (fout / 10000); 204 fvcoiic = foutiic * n; 205 206 mint = fvcoiic / 114285000; 207 if ((mint < 17) || (mint > 63)) 208 printf("ics8n3qv01_calc_parameters: cannot determine mint\n"); 209 210 mfrac = ((unsigned long long)fvcoiic % 114285000LL) * 262144LL 211 / 114285000LL; 212 213 *_mint = mint; 214 *_mfrac = mfrac; 215 *_n = n; 216 } 217 218 static void ics8n3qv01_set(unsigned screen, unsigned int fout) 219 { 220 unsigned int n; 221 unsigned int mint; 222 unsigned int mfrac; 223 unsigned int fout_calc; 224 unsigned long long fout_prog; 225 long long off_ppm; 226 u8 reg0, reg4, reg8, reg12, reg18, reg20; 227 228 fout_calc = ics8n3qv01_get_fout_calc(screen, 1); 229 off_ppm = (fout_calc - ICS8N3QV01_F_DEFAULT_1) * 1000000 230 / ICS8N3QV01_F_DEFAULT_1; 231 printf(" PLL is off by %lld ppm\n", off_ppm); 232 fout_prog = (unsigned long long)fout * (unsigned long long)fout_calc 233 / ICS8N3QV01_F_DEFAULT_1; 234 ics8n3qv01_calc_parameters(fout_prog, &mint, &mfrac, &n); 235 236 reg0 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0) & 0xc0; 237 reg0 |= (mint & 0x1f) << 1; 238 reg0 |= (mfrac >> 17) & 0x01; 239 fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 0, reg0); 240 241 reg4 = mfrac >> 9; 242 fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 4, reg4); 243 244 reg8 = mfrac >> 1; 245 fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 8, reg8); 246 247 reg12 = mfrac << 7; 248 reg12 |= n & 0x7f; 249 fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 12, reg12); 250 251 reg18 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 18) & 0x03; 252 reg18 |= 0x20; 253 fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 18, reg18); 254 255 reg20 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 20) & 0x1f; 256 reg20 |= mint & (1 << 5); 257 fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 20, reg20); 258 } 259 #endif 260 261 static int osd_write_videomem(unsigned screen, unsigned offset, 262 u16 *data, size_t charcount) 263 { 264 unsigned int k; 265 266 for (k = 0; k < charcount; ++k) { 267 if (offset + k >= BUFSIZE) 268 return -1; 269 FPGA_SET_REG(screen, videomem[offset + k], data[k]); 270 } 271 272 return charcount; 273 } 274 275 static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 276 { 277 unsigned screen; 278 279 for (screen = 0; screen <= max_osd_screen; ++screen) { 280 unsigned x; 281 unsigned y; 282 unsigned charcount; 283 unsigned len; 284 u8 color; 285 unsigned int k; 286 u16 buf[BUFSIZE]; 287 char *text; 288 int res; 289 290 if (argc < 5) { 291 cmd_usage(cmdtp); 292 return 1; 293 } 294 295 x = simple_strtoul(argv[1], NULL, 16); 296 y = simple_strtoul(argv[2], NULL, 16); 297 color = simple_strtoul(argv[3], NULL, 16); 298 text = argv[4]; 299 charcount = strlen(text); 300 len = (charcount > BUFSIZE) ? BUFSIZE : charcount; 301 302 for (k = 0; k < len; ++k) 303 buf[k] = (text[k] << 8) | color; 304 305 res = osd_write_videomem(screen, y * BASE_WIDTH + x, buf, len); 306 if (res < 0) 307 return res; 308 } 309 310 return 0; 311 } 312 313 int osd_probe(unsigned screen) 314 { 315 u16 version; 316 u16 features; 317 unsigned width; 318 unsigned height; 319 u8 value; 320 #ifdef CONFIG_SYS_CH7301 321 int old_bus = i2c_get_bus_num(); 322 #endif 323 324 FPGA_GET_REG(0, osd.version, &version); 325 FPGA_GET_REG(0, osd.features, &features); 326 327 width = ((features & 0x3f00) >> 8) + 1; 328 height = (features & 0x001f) + 1; 329 330 printf("OSD%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n", 331 screen, version/100, version%100, width, height); 332 333 #ifdef CONFIG_SYS_CH7301 334 i2c_set_bus_num(ch7301_i2c[screen]); 335 value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID); 336 if (value != 0x17) { 337 printf(" Probing CH7301 failed, DID %02x\n", value); 338 i2c_set_bus_num(old_bus); 339 return -1; 340 } 341 i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08); 342 i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16); 343 i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60); 344 i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09); 345 i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0); 346 i2c_set_bus_num(old_bus); 347 #endif 348 349 #ifdef CONFIG_SYS_MPC92469AC 350 mpc92469ac_set(screen, PIXCLK_640_480_60); 351 #endif 352 353 #ifdef CONFIG_SYS_ICS8N3QV01 354 ics8n3qv01_set(screen, PIXCLK_640_480_60); 355 #endif 356 357 #ifdef CONFIG_SYS_SIL1178 358 value = fpga_iic_read(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x02); 359 if (value != 0x06) { 360 printf(" Probing CH7301 SIL1178, DEV_IDL %02x\n", value); 361 return -1; 362 } 363 /* magic initialization sequence adapted from datasheet */ 364 fpga_iic_write(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36); 365 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44); 366 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c); 367 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10); 368 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80); 369 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30); 370 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89); 371 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60); 372 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36); 373 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37); 374 #endif 375 376 FPGA_SET_REG(screen, videocontrol, 0x0002); 377 FPGA_SET_REG(screen, osd.control, 0x0049); 378 379 FPGA_SET_REG(screen, osd.xy_size, ((32 - 1) << 8) | (16 - 1)); 380 FPGA_SET_REG(screen, osd.x_pos, 0x007f); 381 FPGA_SET_REG(screen, osd.y_pos, 0x005f); 382 383 if (screen > max_osd_screen) 384 max_osd_screen = screen; 385 386 return 0; 387 } 388 389 int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 390 { 391 unsigned screen; 392 393 for (screen = 0; screen <= max_osd_screen; ++screen) { 394 unsigned x; 395 unsigned y; 396 unsigned k; 397 u16 buffer[BASE_WIDTH]; 398 char *rp; 399 u16 *wp = buffer; 400 unsigned count = (argc > 4) ? 401 simple_strtoul(argv[4], NULL, 16) : 1; 402 403 if ((argc < 4) || (strlen(argv[3]) % 4)) { 404 cmd_usage(cmdtp); 405 return 1; 406 } 407 408 x = simple_strtoul(argv[1], NULL, 16); 409 y = simple_strtoul(argv[2], NULL, 16); 410 rp = argv[3]; 411 412 413 while (*rp) { 414 char substr[5]; 415 416 memcpy(substr, rp, 4); 417 substr[4] = 0; 418 *wp = simple_strtoul(substr, NULL, 16); 419 420 rp += 4; 421 wp++; 422 if (wp - buffer > BASE_WIDTH) 423 break; 424 } 425 426 for (k = 0; k < count; ++k) { 427 unsigned offset = 428 y * BASE_WIDTH + x + k * (wp - buffer); 429 osd_write_videomem(screen, offset, buffer, 430 wp - buffer); 431 } 432 } 433 434 return 0; 435 } 436 437 U_BOOT_CMD( 438 osdw, 5, 0, osd_write, 439 "write 16-bit hex encoded buffer to osd memory", 440 "pos_x pos_y buffer count\n" 441 ); 442 443 U_BOOT_CMD( 444 osdp, 5, 0, osd_print, 445 "write ASCII buffer to osd memory", 446 "pos_x pos_y color text\n" 447 ); 448