1*a3f9d6c7SDirk Eibach /*
2*a3f9d6c7SDirk Eibach * (C) Copyright 2014
3*a3f9d6c7SDirk Eibach * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
4*a3f9d6c7SDirk Eibach *
5*a3f9d6c7SDirk Eibach * SPDX-License-Identifier: GPL-2.0+
6*a3f9d6c7SDirk Eibach */
7*a3f9d6c7SDirk Eibach
8*a3f9d6c7SDirk Eibach /* Chrontel CH7301C DVI Transmitter */
9*a3f9d6c7SDirk Eibach
10*a3f9d6c7SDirk Eibach #include <common.h>
11*a3f9d6c7SDirk Eibach #include <asm/io.h>
12*a3f9d6c7SDirk Eibach #include <errno.h>
13*a3f9d6c7SDirk Eibach #include <i2c.h>
14*a3f9d6c7SDirk Eibach
15*a3f9d6c7SDirk Eibach #define CH7301_I2C_ADDR 0x75
16*a3f9d6c7SDirk Eibach
17*a3f9d6c7SDirk Eibach enum {
18*a3f9d6c7SDirk Eibach CH7301_CM = 0x1c, /* Clock Mode Register */
19*a3f9d6c7SDirk Eibach CH7301_IC = 0x1d, /* Input Clock Register */
20*a3f9d6c7SDirk Eibach CH7301_GPIO = 0x1e, /* GPIO Control Register */
21*a3f9d6c7SDirk Eibach CH7301_IDF = 0x1f, /* Input Data Format Register */
22*a3f9d6c7SDirk Eibach CH7301_CD = 0x20, /* Connection Detect Register */
23*a3f9d6c7SDirk Eibach CH7301_DC = 0x21, /* DAC Control Register */
24*a3f9d6c7SDirk Eibach CH7301_HPD = 0x23, /* Hot Plug Detection Register */
25*a3f9d6c7SDirk Eibach CH7301_TCTL = 0x31, /* DVI Control Input Register */
26*a3f9d6c7SDirk Eibach CH7301_TPCP = 0x33, /* DVI PLL Charge Pump Ctrl Register */
27*a3f9d6c7SDirk Eibach CH7301_TPD = 0x34, /* DVI PLL Divide Register */
28*a3f9d6c7SDirk Eibach CH7301_TPVT = 0x35, /* DVI PLL Supply Control Register */
29*a3f9d6c7SDirk Eibach CH7301_TPF = 0x36, /* DVI PLL Filter Register */
30*a3f9d6c7SDirk Eibach CH7301_TCT = 0x37, /* DVI Clock Test Register */
31*a3f9d6c7SDirk Eibach CH7301_TSTP = 0x48, /* Test Pattern Register */
32*a3f9d6c7SDirk Eibach CH7301_PM = 0x49, /* Power Management register */
33*a3f9d6c7SDirk Eibach CH7301_VID = 0x4a, /* Version ID Register */
34*a3f9d6c7SDirk Eibach CH7301_DID = 0x4b, /* Device ID Register */
35*a3f9d6c7SDirk Eibach CH7301_DSP = 0x56, /* DVI Sync polarity Register */
36*a3f9d6c7SDirk Eibach };
37*a3f9d6c7SDirk Eibach
38*a3f9d6c7SDirk Eibach int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C;
39*a3f9d6c7SDirk Eibach
ch7301_probe(unsigned screen,bool power)40*a3f9d6c7SDirk Eibach int ch7301_probe(unsigned screen, bool power)
41*a3f9d6c7SDirk Eibach {
42*a3f9d6c7SDirk Eibach u8 value;
43*a3f9d6c7SDirk Eibach
44*a3f9d6c7SDirk Eibach i2c_set_bus_num(ch7301_i2c[screen]);
45*a3f9d6c7SDirk Eibach if (i2c_probe(CH7301_I2C_ADDR))
46*a3f9d6c7SDirk Eibach return -1;
47*a3f9d6c7SDirk Eibach
48*a3f9d6c7SDirk Eibach value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
49*a3f9d6c7SDirk Eibach if (value != 0x17)
50*a3f9d6c7SDirk Eibach return -1;
51*a3f9d6c7SDirk Eibach
52*a3f9d6c7SDirk Eibach if (power) {
53*a3f9d6c7SDirk Eibach i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08);
54*a3f9d6c7SDirk Eibach i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16);
55*a3f9d6c7SDirk Eibach i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
56*a3f9d6c7SDirk Eibach i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
57*a3f9d6c7SDirk Eibach i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
58*a3f9d6c7SDirk Eibach } else {
59*a3f9d6c7SDirk Eibach i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x00);
60*a3f9d6c7SDirk Eibach i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0x01);
61*a3f9d6c7SDirk Eibach }
62*a3f9d6c7SDirk Eibach
63*a3f9d6c7SDirk Eibach return 0;
64*a3f9d6c7SDirk Eibach }
65