1*15f05610SDirk Eibach struct ihs_fpga { 2*15f05610SDirk Eibach u32 reflection_low; /* 0x0000 */ 3*15f05610SDirk Eibach u32 versions; /* 0x0004 */ 4*15f05610SDirk Eibach u32 fpga_version; /* 0x0008 */ 5*15f05610SDirk Eibach u32 fpga_features; /* 0x000c */ 6*15f05610SDirk Eibach u32 reserved0[4]; /* 0x0010 */ 7*15f05610SDirk Eibach u32 control; /* 0x0020 */ 8*15f05610SDirk Eibach u32 reserved1[375]; /* 0x0024 */ 9*15f05610SDirk Eibach u32 qsgmii_port_state[80]; /* 0x0600 */ 10*15f05610SDirk Eibach }; 11*15f05610SDirk Eibach 12*15f05610SDirk Eibach void print_hydra_version(uint index); 13*15f05610SDirk Eibach void hydra_initialize(void); 14*15f05610SDirk Eibach struct ihs_fpga *get_fpga(void); 15