1 /* 2 * Copyright (C) 2013 Gateworks Corporation 3 * 4 * Author: Tim Harvey <tharvey@gateworks.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <asm/errno.h> 10 #include <common.h> 11 #include <i2c.h> 12 #include <linux/ctype.h> 13 14 #include "gsc.h" 15 16 /* 17 * The Gateworks System Controller will fail to ACK a master transaction if 18 * it is busy, which can occur during its 1HZ timer tick while reading ADC's. 19 * When this does occur, it will never be busy long enough to fail more than 20 * 2 back-to-back transfers. Thus we wrap i2c_read and i2c_write with 21 * 3 retries. 22 */ 23 int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) 24 { 25 int retry = 3; 26 int n = 0; 27 int ret; 28 29 while (n++ < retry) { 30 ret = i2c_read(chip, addr, alen, buf, len); 31 if (!ret) 32 break; 33 debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr, 34 n, ret); 35 if (ret != -ENODEV) 36 break; 37 mdelay(10); 38 } 39 return ret; 40 } 41 42 int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) 43 { 44 int retry = 3; 45 int n = 0; 46 int ret; 47 48 while (n++ < retry) { 49 ret = i2c_write(chip, addr, alen, buf, len); 50 if (!ret) 51 break; 52 debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr, 53 n, ret); 54 if (ret != -ENODEV) 55 break; 56 mdelay(10); 57 } 58 mdelay(100); 59 return ret; 60 } 61 62 #ifdef CONFIG_CMD_GSC 63 static void read_hwmon(const char *name, uint reg, uint size) 64 { 65 unsigned char buf[3]; 66 uint ui; 67 68 printf("%-8s:", name); 69 memset(buf, 0, sizeof(buf)); 70 if (gsc_i2c_read(GSC_HWMON_ADDR, reg, 1, buf, size)) { 71 puts("fRD\n"); 72 } else { 73 ui = buf[0] | (buf[1]<<8) | (buf[2]<<16); 74 if (ui == 0xffffff) 75 puts("invalid\n"); 76 else 77 printf("%d\n", ui); 78 } 79 } 80 81 int do_gsc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 82 { 83 const char *model = getenv("model"); 84 85 i2c_set_bus_num(0); 86 read_hwmon("Temp", GSC_HWMON_TEMP, 2); 87 read_hwmon("VIN", GSC_HWMON_VIN, 3); 88 read_hwmon("VBATT", GSC_HWMON_VBATT, 3); 89 read_hwmon("VDD_3P3", GSC_HWMON_VDD_3P3, 3); 90 read_hwmon("VDD_ARM", GSC_HWMON_VDD_CORE, 3); 91 read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3); 92 read_hwmon("VDD_HIGH", GSC_HWMON_VDD_HIGH, 3); 93 read_hwmon("VDD_DDR", GSC_HWMON_VDD_DDR, 3); 94 read_hwmon("VDD_5P0", GSC_HWMON_VDD_5P0, 3); 95 read_hwmon("VDD_2P5", GSC_HWMON_VDD_2P5, 3); 96 read_hwmon("VDD_1P8", GSC_HWMON_VDD_1P8, 3); 97 read_hwmon("VDD_IO2", GSC_HWMON_VDD_IO2, 3); 98 switch (model[3]) { 99 case '1': /* GW51xx */ 100 read_hwmon("VDD_IO3", GSC_HWMON_VDD_IO4, 3); /* -C rev */ 101 break; 102 case '2': /* GW52xx */ 103 break; 104 case '3': /* GW53xx */ 105 read_hwmon("VDD_IO4", GSC_HWMON_VDD_IO4, 3); /* -C rev */ 106 read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3, 3); 107 break; 108 case '4': /* GW54xx */ 109 read_hwmon("VDD_IO3", GSC_HWMON_VDD_IO4, 3); /* -C rev */ 110 read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3, 3); 111 break; 112 case '5': /* GW55xx */ 113 break; 114 } 115 return 0; 116 } 117 118 U_BOOT_CMD(gsc, 1, 1, do_gsc, 119 "GSC test", 120 "" 121 ); 122 123 #endif /* CONFIG_CMD_GSC */ 124