10b2e13d9SChunhe Lan /* 20b2e13d9SChunhe Lan * Copyright 2014 Freescale Semiconductor, Inc. 30b2e13d9SChunhe Lan * 40b2e13d9SChunhe Lan * SPDX-License-Identifier: GPL-2.0+ 50b2e13d9SChunhe Lan */ 60b2e13d9SChunhe Lan 70b2e13d9SChunhe Lan #ifndef __DDR_H__ 80b2e13d9SChunhe Lan #define __DDR_H__ 90b2e13d9SChunhe Lan struct board_specific_parameters { 100b2e13d9SChunhe Lan u32 n_ranks; 110b2e13d9SChunhe Lan u32 datarate_mhz_high; 120b2e13d9SChunhe Lan u32 rank_gb; 130b2e13d9SChunhe Lan u32 clk_adjust; 140b2e13d9SChunhe Lan u32 wrlvl_start; 150b2e13d9SChunhe Lan u32 wrlvl_ctl_2; 160b2e13d9SChunhe Lan u32 wrlvl_ctl_3; 170b2e13d9SChunhe Lan }; 180b2e13d9SChunhe Lan 190b2e13d9SChunhe Lan /* 200b2e13d9SChunhe Lan * These tables contain all valid speeds we want to override with board 210b2e13d9SChunhe Lan * specific parameters. datarate_mhz_high values need to be in ascending order 220b2e13d9SChunhe Lan * for each n_ranks group. 230b2e13d9SChunhe Lan */ 240b2e13d9SChunhe Lan static const struct board_specific_parameters udimm0[] = { 250b2e13d9SChunhe Lan /* 260b2e13d9SChunhe Lan * memory controller 0 270b2e13d9SChunhe Lan * num| hi| rank| clk| wrlvl | wrlvl | wrlvl 280b2e13d9SChunhe Lan * ranks| mhz| GB |adjst| start | ctl2 | ctl3 290b2e13d9SChunhe Lan */ 30*e04f9d0cSShengzhou Liu {2, 1350, 4, 8, 8, 0x0809090b, 0x0c0c0d0a}, 31*e04f9d0cSShengzhou Liu {2, 1350, 0, 10, 7, 0x0709090b, 0x0c0c0d09}, 32*e04f9d0cSShengzhou Liu {2, 1666, 4, 8, 8, 0x080a0a0d, 0x0d10100b}, 33*e04f9d0cSShengzhou Liu {2, 1666, 0, 10, 7, 0x080a0a0c, 0x0d0d0e0a}, 34*e04f9d0cSShengzhou Liu {2, 1900, 0, 8, 8, 0x090a0b0e, 0x0f11120c}, 35*e04f9d0cSShengzhou Liu {2, 2140, 0, 8, 8, 0x090a0b0e, 0x0f11120c}, 36*e04f9d0cSShengzhou Liu {1, 1350, 0, 10, 8, 0x0809090b, 0x0c0c0d0a}, 37*e04f9d0cSShengzhou Liu {1, 1700, 0, 10, 8, 0x080a0a0c, 0x0c0d0e0a}, 38*e04f9d0cSShengzhou Liu {1, 1900, 0, 8, 8, 0x080a0a0c, 0x0e0e0f0a}, 39*e04f9d0cSShengzhou Liu {1, 2140, 0, 8, 8, 0x090a0b0c, 0x0e0f100b}, 400b2e13d9SChunhe Lan {} 410b2e13d9SChunhe Lan }; 420b2e13d9SChunhe Lan 430b2e13d9SChunhe Lan static const struct board_specific_parameters rdimm0[] = { 440b2e13d9SChunhe Lan /* 450b2e13d9SChunhe Lan * memory controller 0 460b2e13d9SChunhe Lan * num| hi| rank| clk| wrlvl | wrlvl | wrlvl 470b2e13d9SChunhe Lan * ranks| mhz| GB |adjst| start | ctl2 | ctl3 480b2e13d9SChunhe Lan */ 49*e04f9d0cSShengzhou Liu {4, 1350, 0, 10, 9, 0x08070605, 0x06070806}, 50*e04f9d0cSShengzhou Liu {4, 1666, 0, 10, 11, 0x0a080706, 0x07090906}, 51*e04f9d0cSShengzhou Liu {4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07}, 52*e04f9d0cSShengzhou Liu {2, 1350, 0, 10, 9, 0x08070605, 0x06070806}, 53*e04f9d0cSShengzhou Liu {2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06}, 54*e04f9d0cSShengzhou Liu {2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07}, 55*e04f9d0cSShengzhou Liu {1, 1350, 0, 10, 9, 0x08070605, 0x06070806}, 56*e04f9d0cSShengzhou Liu {1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06}, 57*e04f9d0cSShengzhou Liu {1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07}, 580b2e13d9SChunhe Lan {} 590b2e13d9SChunhe Lan }; 600b2e13d9SChunhe Lan 610b2e13d9SChunhe Lan /* 620b2e13d9SChunhe Lan * The three slots have slightly different timing. The center values are good 630b2e13d9SChunhe Lan * for all slots. We use identical speed tables for them. In future use, if 640b2e13d9SChunhe Lan * DIMMs require separated tables, make more entries as needed. 650b2e13d9SChunhe Lan */ 660b2e13d9SChunhe Lan static const struct board_specific_parameters *udimms[] = { 670b2e13d9SChunhe Lan udimm0, 680b2e13d9SChunhe Lan }; 690b2e13d9SChunhe Lan 700b2e13d9SChunhe Lan /* 710b2e13d9SChunhe Lan * The three slots have slightly different timing. See comments above. 720b2e13d9SChunhe Lan */ 730b2e13d9SChunhe Lan static const struct board_specific_parameters *rdimms[] = { 740b2e13d9SChunhe Lan rdimm0, 750b2e13d9SChunhe Lan }; 760b2e13d9SChunhe Lan 770b2e13d9SChunhe Lan 780b2e13d9SChunhe Lan #endif 79