1 /* 2 * Copyright 2012 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <netdev.h> 26 #include <asm/mmu.h> 27 #include <asm/processor.h> 28 #include <asm/cache.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/fsl_law.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/fsl_serdes.h> 33 #include <asm/fsl_portals.h> 34 #include <asm/fsl_liodn.h> 35 #include <malloc.h> 36 #include <fm_eth.h> 37 #include <fsl_mdio.h> 38 #include <miiphy.h> 39 #include <phy.h> 40 #include <asm/fsl_dtsec.h> 41 #include <asm/fsl_serdes.h> 42 #include "../common/qixis.h" 43 #include "../common/fman.h" 44 45 #include "t4240qds_qixis.h" 46 47 #define EMI_NONE 0xFFFFFFFF 48 #define EMI1_RGMII 0 49 #define EMI1_SLOT1 1 50 #define EMI1_SLOT2 2 51 #define EMI1_SLOT3 3 52 #define EMI1_SLOT4 4 53 #define EMI1_SLOT5 5 54 #define EMI1_SLOT7 7 55 #define EMI2 8 56 /* Slot6 and Slot8 do not have EMI connections */ 57 58 static int mdio_mux[NUM_FM_PORTS]; 59 60 static const char *mdio_names[] = { 61 "T4240QDS_MDIO0", 62 "T4240QDS_MDIO1", 63 "T4240QDS_MDIO2", 64 "T4240QDS_MDIO3", 65 "T4240QDS_MDIO4", 66 "T4240QDS_MDIO5", 67 "NULL", 68 "T4240QDS_MDIO7", 69 "T4240QDS_10GC", 70 }; 71 72 static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2}; 73 static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4}; 74 static u8 slot_qsgmii_phyaddr[5][4] = { 75 {0, 0, 0, 0},/* not used, to make index match slot No. */ 76 {0, 1, 2, 3}, 77 {4, 5, 6, 7}, 78 {8, 9, 0xa, 0xb}, 79 {0xc, 0xd, 0xe, 0xf}, 80 }; 81 82 static const char *t4240qds_mdio_name_for_muxval(u8 muxval) 83 { 84 return mdio_names[muxval]; 85 } 86 87 struct mii_dev *mii_dev_for_muxval(u8 muxval) 88 { 89 struct mii_dev *bus; 90 const char *name = t4240qds_mdio_name_for_muxval(muxval); 91 92 if (!name) { 93 printf("No bus for muxval %x\n", muxval); 94 return NULL; 95 } 96 97 bus = miiphy_get_dev_by_name(name); 98 99 if (!bus) { 100 printf("No bus by name %s\n", name); 101 return NULL; 102 } 103 104 return bus; 105 } 106 107 struct t4240qds_mdio { 108 u8 muxval; 109 struct mii_dev *realbus; 110 }; 111 112 static void t4240qds_mux_mdio(u8 muxval) 113 { 114 u8 brdcfg4; 115 if ((muxval < 6) || (muxval == 7)) { 116 brdcfg4 = QIXIS_READ(brdcfg[4]); 117 brdcfg4 &= ~BRDCFG4_EMISEL_MASK; 118 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); 119 QIXIS_WRITE(brdcfg[4], brdcfg4); 120 } 121 } 122 123 static int t4240qds_mdio_read(struct mii_dev *bus, int addr, int devad, 124 int regnum) 125 { 126 struct t4240qds_mdio *priv = bus->priv; 127 128 t4240qds_mux_mdio(priv->muxval); 129 130 return priv->realbus->read(priv->realbus, addr, devad, regnum); 131 } 132 133 static int t4240qds_mdio_write(struct mii_dev *bus, int addr, int devad, 134 int regnum, u16 value) 135 { 136 struct t4240qds_mdio *priv = bus->priv; 137 138 t4240qds_mux_mdio(priv->muxval); 139 140 return priv->realbus->write(priv->realbus, addr, devad, regnum, value); 141 } 142 143 static int t4240qds_mdio_reset(struct mii_dev *bus) 144 { 145 struct t4240qds_mdio *priv = bus->priv; 146 147 return priv->realbus->reset(priv->realbus); 148 } 149 150 static int t4240qds_mdio_init(char *realbusname, u8 muxval) 151 { 152 struct t4240qds_mdio *pmdio; 153 struct mii_dev *bus = mdio_alloc(); 154 155 if (!bus) { 156 printf("Failed to allocate T4240QDS MDIO bus\n"); 157 return -1; 158 } 159 160 pmdio = malloc(sizeof(*pmdio)); 161 if (!pmdio) { 162 printf("Failed to allocate T4240QDS private data\n"); 163 free(bus); 164 return -1; 165 } 166 167 bus->read = t4240qds_mdio_read; 168 bus->write = t4240qds_mdio_write; 169 bus->reset = t4240qds_mdio_reset; 170 sprintf(bus->name, t4240qds_mdio_name_for_muxval(muxval)); 171 172 pmdio->realbus = miiphy_get_dev_by_name(realbusname); 173 174 if (!pmdio->realbus) { 175 printf("No bus with name %s\n", realbusname); 176 free(bus); 177 free(pmdio); 178 return -1; 179 } 180 181 pmdio->muxval = muxval; 182 bus->priv = pmdio; 183 184 return mdio_register(bus); 185 } 186 187 void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, 188 enum fm_port port, int offset) 189 { 190 if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { 191 switch (port) { 192 case FM1_DTSEC9: 193 fdt_set_phy_handle(blob, prop, pa, "phy_sgmii4"); 194 break; 195 case FM1_DTSEC10: 196 fdt_set_phy_handle(blob, prop, pa, "phy_sgmii3"); 197 break; 198 case FM2_DTSEC9: 199 fdt_set_phy_handle(blob, prop, pa, "phy_sgmii12"); 200 break; 201 case FM2_DTSEC10: 202 fdt_set_phy_handle(blob, prop, pa, "phy_sgmii11"); 203 break; 204 default: 205 break; 206 } 207 } 208 } 209 210 void fdt_fixup_board_enet(void *fdt) 211 { 212 int i; 213 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 214 u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL; 215 216 prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; 217 for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) { 218 switch (fm_info_get_enet_if(i)) { 219 case PHY_INTERFACE_MODE_SGMII: 220 switch (mdio_mux[i]) { 221 case EMI1_SLOT1: 222 fdt_status_okay_by_alias(fdt, "emi1_slot1"); 223 break; 224 case EMI1_SLOT2: 225 fdt_status_okay_by_alias(fdt, "emi1_slot2"); 226 break; 227 case EMI1_SLOT3: 228 fdt_status_okay_by_alias(fdt, "emi1_slot3"); 229 break; 230 case EMI1_SLOT4: 231 fdt_status_okay_by_alias(fdt, "emi1_slot4"); 232 break; 233 default: 234 break; 235 } 236 break; 237 case PHY_INTERFACE_MODE_XGMII: 238 /* check if it's XFI interface for 10g */ 239 if ((prtcl2 == 56) || (prtcl2 == 57)) { 240 fdt_status_okay_by_alias(fdt, "emi2_xfislot3"); 241 break; 242 } 243 switch (i) { 244 case FM1_10GEC1: 245 fdt_status_okay_by_alias(fdt, "emi2_xauislot1"); 246 break; 247 case FM1_10GEC2: 248 fdt_status_okay_by_alias(fdt, "emi2_xauislot2"); 249 break; 250 case FM2_10GEC1: 251 fdt_status_okay_by_alias(fdt, "emi2_xauislot3"); 252 break; 253 case FM2_10GEC2: 254 fdt_status_okay_by_alias(fdt, "emi2_xauislot4"); 255 break; 256 default: 257 break; 258 } 259 break; 260 default: 261 break; 262 } 263 } 264 } 265 266 int board_eth_init(bd_t *bis) 267 { 268 #if defined(CONFIG_FMAN_ENET) 269 int i, idx, lane, slot; 270 struct memac_mdio_info dtsec_mdio_info; 271 struct memac_mdio_info tgec_mdio_info; 272 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 273 u32 srds_prtcl_s1, srds_prtcl_s2; 274 275 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & 276 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; 277 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; 278 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & 279 FSL_CORENET2_RCWSR4_SRDS2_PRTCL; 280 srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; 281 282 /* Initialize the mdio_mux array so we can recognize empty elements */ 283 for (i = 0; i < NUM_FM_PORTS; i++) 284 mdio_mux[i] = EMI_NONE; 285 286 dtsec_mdio_info.regs = 287 (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR; 288 289 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; 290 291 /* Register the 1G MDIO bus */ 292 fm_memac_mdio_init(bis, &dtsec_mdio_info); 293 294 tgec_mdio_info.regs = 295 (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR; 296 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; 297 298 /* Register the 10G MDIO bus */ 299 fm_memac_mdio_init(bis, &tgec_mdio_info); 300 301 /* Register the muxing front-ends to the MDIO buses */ 302 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII); 303 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); 304 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); 305 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); 306 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); 307 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); 308 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7); 309 t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); 310 311 312 switch (srds_prtcl_s1) { 313 case 1: 314 case 2: 315 case 4: 316 /* XAUI/HiGig in Slot1 and Slot2 */ 317 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); 318 fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR); 319 break; 320 case 28: 321 case 36: 322 /* SGMII in Slot1 and Slot2 */ 323 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]); 324 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]); 325 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]); 326 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]); 327 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]); 328 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]); 329 if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) { 330 fm_info_set_phy_address(FM1_DTSEC9, 331 slot_qsgmii_phyaddr[1][3]); 332 fm_info_set_phy_address(FM1_DTSEC10, 333 slot_qsgmii_phyaddr[1][2]); 334 } 335 break; 336 case 38: 337 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]); 338 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]); 339 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]); 340 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]); 341 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]); 342 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]); 343 if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) { 344 fm_info_set_phy_address(FM1_DTSEC9, 345 slot_qsgmii_phyaddr[1][3]); 346 fm_info_set_phy_address(FM1_DTSEC10, 347 slot_qsgmii_phyaddr[1][2]); 348 } 349 break; 350 case 40: 351 case 46: 352 case 48: 353 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]); 354 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]); 355 if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) { 356 fm_info_set_phy_address(FM1_DTSEC10, 357 slot_qsgmii_phyaddr[1][3]); 358 fm_info_set_phy_address(FM1_DTSEC9, 359 slot_qsgmii_phyaddr[1][2]); 360 } 361 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]); 362 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]); 363 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]); 364 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]); 365 break; 366 default: 367 puts("Invalid SerDes1 protocol for T4240QDS\n"); 368 break; 369 } 370 371 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { 372 idx = i - FM1_DTSEC1; 373 switch (fm_info_get_enet_if(i)) { 374 case PHY_INTERFACE_MODE_SGMII: 375 lane = serdes_get_first_lane(FSL_SRDS_1, 376 SGMII_FM1_DTSEC1 + idx); 377 if (lane < 0) 378 break; 379 slot = lane_to_slot_fsm1[lane]; 380 debug("FM1@DTSEC%u expects SGMII in slot %u\n", 381 idx + 1, slot); 382 if (QIXIS_READ(present2) & (1 << (slot - 1))) 383 fm_disable_port(i); 384 switch (slot) { 385 case 1: 386 mdio_mux[i] = EMI1_SLOT1; 387 fm_info_set_mdio(i, 388 mii_dev_for_muxval(mdio_mux[i])); 389 break; 390 case 2: 391 mdio_mux[i] = EMI1_SLOT2; 392 fm_info_set_mdio(i, 393 mii_dev_for_muxval(mdio_mux[i])); 394 break; 395 }; 396 break; 397 case PHY_INTERFACE_MODE_RGMII: 398 /* FM1 DTSEC5 routes to RGMII with EC2 */ 399 debug("FM1@DTSEC%u is RGMII at address %u\n", 400 idx + 1, 2); 401 if (i == FM1_DTSEC5) 402 fm_info_set_phy_address(i, 2); 403 mdio_mux[i] = EMI1_RGMII; 404 fm_info_set_mdio(i, 405 mii_dev_for_muxval(mdio_mux[i])); 406 break; 407 default: 408 break; 409 } 410 } 411 412 for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { 413 idx = i - FM1_10GEC1; 414 switch (fm_info_get_enet_if(i)) { 415 case PHY_INTERFACE_MODE_XGMII: 416 lane = serdes_get_first_lane(FSL_SRDS_1, 417 XAUI_FM1_MAC9 + idx); 418 if (lane < 0) 419 break; 420 slot = lane_to_slot_fsm1[lane]; 421 if (QIXIS_READ(present2) & (1 << (slot - 1))) 422 fm_disable_port(i); 423 mdio_mux[i] = EMI2; 424 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); 425 break; 426 default: 427 break; 428 } 429 } 430 431 #if (CONFIG_SYS_NUM_FMAN == 2) 432 switch (srds_prtcl_s2) { 433 case 1: 434 case 2: 435 case 4: 436 /* XAUI/HiGig in Slot3 and Slot4 */ 437 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR); 438 fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR); 439 break; 440 case 7: 441 case 13: 442 case 14: 443 case 16: 444 case 22: 445 case 23: 446 case 25: 447 case 26: 448 /* XAUI/HiGig in Slot3, SGMII in Slot4 */ 449 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR); 450 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); 451 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]); 452 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); 453 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); 454 break; 455 case 28: 456 case 36: 457 /* SGMII in Slot3 and Slot4 */ 458 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); 459 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]); 460 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); 461 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); 462 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]); 463 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]); 464 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]); 465 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]); 466 break; 467 case 38: 468 /* QSGMII in Slot3 and Slot4 */ 469 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); 470 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]); 471 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); 472 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); 473 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]); 474 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]); 475 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]); 476 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]); 477 break; 478 case 40: 479 case 46: 480 case 48: 481 /* SGMII in Slot3 */ 482 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]); 483 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]); 484 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]); 485 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]); 486 /* QSGMII in Slot4 */ 487 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); 488 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]); 489 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); 490 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); 491 break; 492 case 50: 493 case 52: 494 case 54: 495 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR); 496 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); 497 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]); 498 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); 499 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); 500 break; 501 case 56: 502 case 57: 503 /* XFI in Slot3, SGMII in Slot4 */ 504 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); 505 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]); 506 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); 507 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); 508 break; 509 default: 510 puts("Invalid SerDes2 protocol for T4240QDS\n"); 511 break; 512 } 513 514 for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { 515 idx = i - FM2_DTSEC1; 516 switch (fm_info_get_enet_if(i)) { 517 case PHY_INTERFACE_MODE_SGMII: 518 lane = serdes_get_first_lane(FSL_SRDS_2, 519 SGMII_FM2_DTSEC1 + idx); 520 if (lane < 0) 521 break; 522 slot = lane_to_slot_fsm2[lane]; 523 debug("FM2@DTSEC%u expects SGMII in slot %u\n", 524 idx + 1, slot); 525 if (QIXIS_READ(present2) & (1 << (slot - 1))) 526 fm_disable_port(i); 527 switch (slot) { 528 case 3: 529 mdio_mux[i] = EMI1_SLOT3; 530 fm_info_set_mdio(i, 531 mii_dev_for_muxval(mdio_mux[i])); 532 break; 533 case 4: 534 mdio_mux[i] = EMI1_SLOT4; 535 fm_info_set_mdio(i, 536 mii_dev_for_muxval(mdio_mux[i])); 537 break; 538 }; 539 break; 540 case PHY_INTERFACE_MODE_RGMII: 541 /* 542 * If DTSEC5 is RGMII, then it's routed via via EC1 to 543 * the first on-board RGMII port. If DTSEC6 is RGMII, 544 * then it's routed via via EC2 to the second on-board 545 * RGMII port. 546 */ 547 debug("FM2@DTSEC%u is RGMII at address %u\n", 548 idx + 1, i == FM2_DTSEC5 ? 1 : 2); 549 fm_info_set_phy_address(i, i == FM2_DTSEC5 ? 1 : 2); 550 mdio_mux[i] = EMI1_RGMII; 551 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); 552 break; 553 default: 554 break; 555 } 556 } 557 558 for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) { 559 idx = i - FM2_10GEC1; 560 switch (fm_info_get_enet_if(i)) { 561 case PHY_INTERFACE_MODE_XGMII: 562 lane = serdes_get_first_lane(FSL_SRDS_2, 563 XAUI_FM2_MAC9 + idx); 564 if (lane < 0) 565 break; 566 slot = lane_to_slot_fsm2[lane]; 567 if (QIXIS_READ(present2) & (1 << (slot - 1))) 568 fm_disable_port(i); 569 mdio_mux[i] = EMI2; 570 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); 571 break; 572 default: 573 break; 574 } 575 } 576 #endif /* CONFIG_SYS_NUM_FMAN */ 577 578 cpu_eth_init(bis); 579 #endif /* CONFIG_FMAN_ENET */ 580 581 return pci_eth_init(bis); 582 } 583