18d67c368SShengzhou Liu /* 28d67c368SShengzhou Liu * Copyright 2014 Freescale Semiconductor 38d67c368SShengzhou Liu * 48d67c368SShengzhou Liu * SPDX-License-Identifier: GPL-2.0+ 58d67c368SShengzhou Liu */ 68d67c368SShengzhou Liu 78d67c368SShengzhou Liu /* 88d67c368SShengzhou Liu * CPLD register set of T2080RDB board-specific. 98d67c368SShengzhou Liu */ 108d67c368SShengzhou Liu struct cpld_data { 118d67c368SShengzhou Liu u8 chip_id1; /* 0x00 - Chip ID1 register */ 128d67c368SShengzhou Liu u8 chip_id2; /* 0x01 - Chip ID2 register */ 138d67c368SShengzhou Liu u8 hw_ver; /* 0x02 - Hardware Revision Register */ 148d67c368SShengzhou Liu u8 sw_ver; /* 0x03 - Software Revision register */ 158d67c368SShengzhou Liu u8 res0[12]; /* 0x04 - 0x0F - not used */ 168d67c368SShengzhou Liu u8 reset_ctl; /* 0x10 - Reset control Register */ 178d67c368SShengzhou Liu u8 flash_csr; /* 0x11 - Flash control and status register */ 188d67c368SShengzhou Liu u8 thermal_csr; /* 0x12 - Thermal control and status register */ 198d67c368SShengzhou Liu u8 led_csr; /* 0x13 - LED control and status register */ 208d67c368SShengzhou Liu u8 sfp_csr; /* 0x14 - SFP+ control and status register */ 218d67c368SShengzhou Liu u8 misc_csr; /* 0x15 - Misc control and status register */ 228d67c368SShengzhou Liu u8 boot_or; /* 0x16 - Boot config override register */ 238d67c368SShengzhou Liu u8 boot_cfg1; /* 0x17 - Boot configuration register 1 */ 248d67c368SShengzhou Liu u8 boot_cfg2; /* 0x18 - Boot configuration register 2 */ 258d67c368SShengzhou Liu } cpld_data_t; 268d67c368SShengzhou Liu 278d67c368SShengzhou Liu u8 cpld_read(unsigned int reg); 288d67c368SShengzhou Liu void cpld_write(unsigned int reg, u8 value); 298d67c368SShengzhou Liu 308d67c368SShengzhou Liu #define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) 318d67c368SShengzhou Liu #define CPLD_WRITE(reg, value) \ 328d67c368SShengzhou Liu cpld_write(offsetof(struct cpld_data, reg), value) 338d67c368SShengzhou Liu 348d67c368SShengzhou Liu /* CPLD on IFC */ 358d67c368SShengzhou Liu #define CPLD_LBMAP_MASK 0x3F 368d67c368SShengzhou Liu #define CPLD_BANK_SEL_MASK 0x07 378d67c368SShengzhou Liu #define CPLD_BANK_OVERRIDE 0x40 38ef531c73SShengzhou Liu #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 39ef531c73SShengzhou Liu #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK 0 */ 408d67c368SShengzhou Liu #define CPLD_LBMAP_RESET 0xFF 418d67c368SShengzhou Liu #define CPLD_LBMAP_SHIFT 0x03 428d67c368SShengzhou Liu #define CPLD_BOOT_SEL 0x80 43*fd3a78a5SShengzhou Liu 44*fd3a78a5SShengzhou Liu /* RSTCON Register */ 45*fd3a78a5SShengzhou Liu #define CPLD_RSTCON_EDC_RST 0x04 46