1*8d67c368SShengzhou Liu /*
2*8d67c368SShengzhou Liu * Copyright 2014 Freescale Semiconductor
3*8d67c368SShengzhou Liu *
4*8d67c368SShengzhou Liu * SPDX-License-Identifier: GPL-2.0+
5*8d67c368SShengzhou Liu *
6*8d67c368SShengzhou Liu * Freescale T2080RDB board-specific CPLD controlling supports.
7*8d67c368SShengzhou Liu */
8*8d67c368SShengzhou Liu
9*8d67c368SShengzhou Liu #include <common.h>
10*8d67c368SShengzhou Liu #include <command.h>
11*8d67c368SShengzhou Liu #include "cpld.h"
12*8d67c368SShengzhou Liu
cpld_read(unsigned int reg)13*8d67c368SShengzhou Liu u8 cpld_read(unsigned int reg)
14*8d67c368SShengzhou Liu {
15*8d67c368SShengzhou Liu void *p = (void *)CONFIG_SYS_CPLD_BASE;
16*8d67c368SShengzhou Liu
17*8d67c368SShengzhou Liu return in_8(p + reg);
18*8d67c368SShengzhou Liu }
19*8d67c368SShengzhou Liu
cpld_write(unsigned int reg,u8 value)20*8d67c368SShengzhou Liu void cpld_write(unsigned int reg, u8 value)
21*8d67c368SShengzhou Liu {
22*8d67c368SShengzhou Liu void *p = (void *)CONFIG_SYS_CPLD_BASE;
23*8d67c368SShengzhou Liu
24*8d67c368SShengzhou Liu out_8(p + reg, value);
25*8d67c368SShengzhou Liu }
26*8d67c368SShengzhou Liu
27*8d67c368SShengzhou Liu /* Set the boot bank to the alternate bank */
cpld_set_altbank(void)28*8d67c368SShengzhou Liu void cpld_set_altbank(void)
29*8d67c368SShengzhou Liu {
30*8d67c368SShengzhou Liu u8 reg = CPLD_READ(flash_csr);
31*8d67c368SShengzhou Liu
32*8d67c368SShengzhou Liu reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK;
33*8d67c368SShengzhou Liu CPLD_WRITE(flash_csr, reg);
34*8d67c368SShengzhou Liu CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET);
35*8d67c368SShengzhou Liu }
36*8d67c368SShengzhou Liu
37*8d67c368SShengzhou Liu /* Set the boot bank to the default bank */
cpld_set_defbank(void)38*8d67c368SShengzhou Liu void cpld_set_defbank(void)
39*8d67c368SShengzhou Liu {
40*8d67c368SShengzhou Liu u8 reg = CPLD_READ(flash_csr);
41*8d67c368SShengzhou Liu
42*8d67c368SShengzhou Liu reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK;
43*8d67c368SShengzhou Liu CPLD_WRITE(flash_csr, reg);
44*8d67c368SShengzhou Liu CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET);
45*8d67c368SShengzhou Liu }
46*8d67c368SShengzhou Liu
do_cpld(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])47*8d67c368SShengzhou Liu int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
48*8d67c368SShengzhou Liu {
49*8d67c368SShengzhou Liu int rc = 0;
50*8d67c368SShengzhou Liu
51*8d67c368SShengzhou Liu if (argc <= 1)
52*8d67c368SShengzhou Liu return cmd_usage(cmdtp);
53*8d67c368SShengzhou Liu
54*8d67c368SShengzhou Liu if (strcmp(argv[1], "reset") == 0) {
55*8d67c368SShengzhou Liu if (strcmp(argv[2], "altbank") == 0)
56*8d67c368SShengzhou Liu cpld_set_altbank();
57*8d67c368SShengzhou Liu else
58*8d67c368SShengzhou Liu cpld_set_defbank();
59*8d67c368SShengzhou Liu } else {
60*8d67c368SShengzhou Liu rc = cmd_usage(cmdtp);
61*8d67c368SShengzhou Liu }
62*8d67c368SShengzhou Liu
63*8d67c368SShengzhou Liu return rc;
64*8d67c368SShengzhou Liu }
65*8d67c368SShengzhou Liu
66*8d67c368SShengzhou Liu U_BOOT_CMD(
67*8d67c368SShengzhou Liu cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
68*8d67c368SShengzhou Liu "Reset the board or alternate bank",
69*8d67c368SShengzhou Liu "reset: reset to default bank\n"
70*8d67c368SShengzhou Liu "cpld reset altbank: reset to alternate bank\n"
71*8d67c368SShengzhou Liu );
72