1062ef1a6SPriyanka Jain /* 2062ef1a6SPriyanka Jain * Copyright 2013 Freescale Semiconductor, Inc. 3062ef1a6SPriyanka Jain * 4062ef1a6SPriyanka Jain * SPDX-License-Identifier: GPL-2.0+ 5062ef1a6SPriyanka Jain */ 6062ef1a6SPriyanka Jain 7062ef1a6SPriyanka Jain #include <common.h> 8062ef1a6SPriyanka Jain #include <asm/fsl_law.h> 9062ef1a6SPriyanka Jain #include <asm/mmu.h> 10062ef1a6SPriyanka Jain 11062ef1a6SPriyanka Jain struct law_entry law_table[] = { 12*e856bdcfSMasahiro Yamada #ifdef CONFIG_MTD_NOR_FLASH 13062ef1a6SPriyanka Jain SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), 14062ef1a6SPriyanka Jain #endif 15062ef1a6SPriyanka Jain #ifdef CONFIG_SYS_BMAN_MEM_PHYS 16062ef1a6SPriyanka Jain SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), 17062ef1a6SPriyanka Jain #endif 18062ef1a6SPriyanka Jain #ifdef CONFIG_SYS_QMAN_MEM_PHYS 19062ef1a6SPriyanka Jain SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), 20062ef1a6SPriyanka Jain #endif 21062ef1a6SPriyanka Jain #ifdef CONFIG_SYS_CPLD_BASE_PHYS 22062ef1a6SPriyanka Jain SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), 23062ef1a6SPriyanka Jain #endif 24062ef1a6SPriyanka Jain #ifdef CONFIG_SYS_DCSRBAR_PHYS 25062ef1a6SPriyanka Jain SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), 26062ef1a6SPriyanka Jain #endif 27062ef1a6SPriyanka Jain #ifdef CONFIG_SYS_NAND_BASE_PHYS 28062ef1a6SPriyanka Jain SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), 29062ef1a6SPriyanka Jain #endif 30062ef1a6SPriyanka Jain }; 31062ef1a6SPriyanka Jain 32062ef1a6SPriyanka Jain int num_law_entries = ARRAY_SIZE(law_table); 33