155153d6cSPrabhakar Kushwaha /** 255153d6cSPrabhakar Kushwaha * Copyright 2013 Freescale Semiconductor 355153d6cSPrabhakar Kushwaha * 455153d6cSPrabhakar Kushwaha * SPDX-License-Identifier: GPL-2.0+ 555153d6cSPrabhakar Kushwaha * 655153d6cSPrabhakar Kushwaha * This file provides support for the ngPIXIS, a board-specific FPGA used on 755153d6cSPrabhakar Kushwaha * some Freescale reference boards. 855153d6cSPrabhakar Kushwaha */ 955153d6cSPrabhakar Kushwaha 1055153d6cSPrabhakar Kushwaha /* 1155153d6cSPrabhakar Kushwaha * CPLD register set. Feel free to add board-specific #ifdefs where necessary. 1255153d6cSPrabhakar Kushwaha */ 1355153d6cSPrabhakar Kushwaha struct cpld_data { 1455153d6cSPrabhakar Kushwaha u8 cpld_ver; /* 0x00 - CPLD Major Revision Register */ 1555153d6cSPrabhakar Kushwaha u8 cpld_ver_sub; /* 0x01 - CPLD Minor Revision Register */ 1655153d6cSPrabhakar Kushwaha u8 hw_ver; /* 0x02 - Hardware Revision Register */ 1755153d6cSPrabhakar Kushwaha u8 sw_ver; /* 0x03 - Software Revision register */ 1855153d6cSPrabhakar Kushwaha u8 res0[12]; /* 0x04 - 0x0F - not used */ 1955153d6cSPrabhakar Kushwaha u8 reset_ctl1; /* 0x10 - Reset control Register1 */ 2055153d6cSPrabhakar Kushwaha u8 reset_ctl2; /* 0x11 - Reset control Register2 */ 2155153d6cSPrabhakar Kushwaha u8 int_status; /* 0x12 - Interrupt status Register */ 2255153d6cSPrabhakar Kushwaha u8 flash_ctl_status; /* 0x13 - Flash control and status register */ 2355153d6cSPrabhakar Kushwaha u8 fan_ctl_status; /* 0x14 - Fan control and status register */ 24*78e56995SYork Sun #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) 254b6067aeSPriyanka Jain u8 int_mask; /* 0x15 - Interrupt mask Register */ 264b6067aeSPriyanka Jain #else 2755153d6cSPrabhakar Kushwaha u8 led_ctl_status; /* 0x15 - LED control and status register */ 284b6067aeSPriyanka Jain #endif 2955153d6cSPrabhakar Kushwaha u8 sfp_ctl_status; /* 0x16 - SFP control and status register */ 3055153d6cSPrabhakar Kushwaha u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/ 3155153d6cSPrabhakar Kushwaha u8 boot_override; /* 0x18 - Boot override register */ 3255153d6cSPrabhakar Kushwaha u8 boot_config1; /* 0x19 - Boot config override register*/ 3355153d6cSPrabhakar Kushwaha u8 boot_config2; /* 0x1A - Boot config override register*/ 3455153d6cSPrabhakar Kushwaha } cpld_data_t; 3555153d6cSPrabhakar Kushwaha 3655153d6cSPrabhakar Kushwaha 3755153d6cSPrabhakar Kushwaha /* Pointer to the CPLD register set */ 3855153d6cSPrabhakar Kushwaha 3955153d6cSPrabhakar Kushwaha u8 cpld_read(unsigned int reg); 4055153d6cSPrabhakar Kushwaha void cpld_write(unsigned int reg, u8 value); 4155153d6cSPrabhakar Kushwaha 4255153d6cSPrabhakar Kushwaha #define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) 4355153d6cSPrabhakar Kushwaha #define CPLD_WRITE(reg, value)\ 4455153d6cSPrabhakar Kushwaha cpld_write(offsetof(struct cpld_data, reg), value) 454b6067aeSPriyanka Jain #define MISC_CTL_SG_SEL 0x80 464b6067aeSPriyanka Jain #define MISC_CTL_AURORA_SEL 0x02 47d4683776SZhao Qiang #define MISC_MUX_QE_TDM 0xc0 48