148c6f328SShengzhou Liu /* 248c6f328SShengzhou Liu * Copyright 2014 Freescale Semiconductor, Inc. 348c6f328SShengzhou Liu * 448c6f328SShengzhou Liu * SPDX-License-Identifier: GPL-2.0+ 548c6f328SShengzhou Liu */ 648c6f328SShengzhou Liu 748c6f328SShengzhou Liu #include <common.h> 848c6f328SShengzhou Liu #include <asm/fsl_law.h> 948c6f328SShengzhou Liu #include <asm/mmu.h> 1048c6f328SShengzhou Liu 1148c6f328SShengzhou Liu struct law_entry law_table[] = { 12*e856bdcfSMasahiro Yamada #ifdef CONFIG_MTD_NOR_FLASH 1348c6f328SShengzhou Liu SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), 1448c6f328SShengzhou Liu #endif 1548c6f328SShengzhou Liu #ifdef CONFIG_SYS_BMAN_MEM_PHYS 1648c6f328SShengzhou Liu SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), 1748c6f328SShengzhou Liu #endif 1848c6f328SShengzhou Liu #ifdef CONFIG_SYS_QMAN_MEM_PHYS 1948c6f328SShengzhou Liu SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), 2048c6f328SShengzhou Liu #endif 2148c6f328SShengzhou Liu #ifdef CONFIG_SYS_CPLD_BASE_PHYS 2248c6f328SShengzhou Liu SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), 2348c6f328SShengzhou Liu #endif 2448c6f328SShengzhou Liu #ifdef CONFIG_SYS_DCSRBAR_PHYS 2548c6f328SShengzhou Liu SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), 2648c6f328SShengzhou Liu #endif 2748c6f328SShengzhou Liu #ifdef CONFIG_SYS_NAND_BASE_PHYS 2848c6f328SShengzhou Liu SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), 2948c6f328SShengzhou Liu #endif 3048c6f328SShengzhou Liu }; 3148c6f328SShengzhou Liu 3248c6f328SShengzhou Liu int num_law_entries = ARRAY_SIZE(law_table); 33