148c6f328SShengzhou Liu /** 248c6f328SShengzhou Liu * Copyright 2014 Freescale Semiconductor 348c6f328SShengzhou Liu * 448c6f328SShengzhou Liu * SPDX-License-Identifier: GPL-2.0+ 548c6f328SShengzhou Liu * 648c6f328SShengzhou Liu */ 748c6f328SShengzhou Liu 848c6f328SShengzhou Liu struct cpld_data { 948c6f328SShengzhou Liu u8 cpld_ver; /* 0x00 - CPLD Major Revision Register */ 1048c6f328SShengzhou Liu u8 cpld_ver_sub; /* 0x01 - CPLD Minor Revision Register */ 1148c6f328SShengzhou Liu u8 hw_ver; /* 0x02 - Hardware Revision Register */ 1248c6f328SShengzhou Liu u8 sw_ver; /* 0x03 - Software Revision register */ 1348c6f328SShengzhou Liu u8 res0[12]; /* 0x04 - 0x0F - not used */ 1448c6f328SShengzhou Liu u8 reset_ctl1; /* 0x10 - Reset control Register1 */ 1548c6f328SShengzhou Liu u8 reset_ctl2; /* 0x11 - Reset control Register2 */ 1648c6f328SShengzhou Liu u8 int_status; /* 0x12 - Interrupt status Register */ 1748c6f328SShengzhou Liu u8 flash_csr; /* 0x13 - Flash control and status register */ 1848c6f328SShengzhou Liu u8 fan_ctl_status; /* 0x14 - Fan control and status register */ 1948c6f328SShengzhou Liu u8 led_ctl_status; /* 0x15 - LED control and status register */ 2048c6f328SShengzhou Liu u8 sfp_ctl_status; /* 0x16 - SFP control and status register */ 2148c6f328SShengzhou Liu u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/ 2248c6f328SShengzhou Liu u8 boot_override; /* 0x18 - Boot override register */ 2348c6f328SShengzhou Liu u8 boot_config1; /* 0x19 - Boot config override register*/ 2448c6f328SShengzhou Liu u8 boot_config2; /* 0x1A - Boot config override register*/ 2548c6f328SShengzhou Liu } cpld_data_t; 2648c6f328SShengzhou Liu 2748c6f328SShengzhou Liu 2848c6f328SShengzhou Liu /* Pointer to the CPLD register set */ 2948c6f328SShengzhou Liu 3048c6f328SShengzhou Liu u8 cpld_read(unsigned int reg); 3148c6f328SShengzhou Liu void cpld_write(unsigned int reg, u8 value); 3248c6f328SShengzhou Liu 3348c6f328SShengzhou Liu #define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) 3448c6f328SShengzhou Liu #define CPLD_WRITE(reg, value)\ 3548c6f328SShengzhou Liu cpld_write(offsetof(struct cpld_data, reg), value) 3648c6f328SShengzhou Liu 3748c6f328SShengzhou Liu /* CPLD on IFC */ 3848c6f328SShengzhou Liu #define CPLD_LBMAP_MASK 0x3F 3948c6f328SShengzhou Liu #define CPLD_BANK_SEL_MASK 0x07 4048c6f328SShengzhou Liu #define CPLD_BANK_OVERRIDE 0x40 4148c6f328SShengzhou Liu #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 4248c6f328SShengzhou Liu #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK 0 */ 4348c6f328SShengzhou Liu #define CPLD_LBMAP_RESET 0xFF 4448c6f328SShengzhou Liu #define CPLD_LBMAP_SHIFT 0x03 4548c6f328SShengzhou Liu #define CPLD_BOOT_SEL 0x80 46*e26416a3SShengzhou Liu 47*e26416a3SShengzhou Liu #define CPLD_PCIE_SGMII_MUX 0x80 48*e26416a3SShengzhou Liu #define CPLD_OVERRIDE_BOOT_EN 0x01 49*e26416a3SShengzhou Liu #define CPLD_OVERRIDE_MUX_EN 0x02 /* PCIE/2.5G-SGMII mux override enable */ 50