1*48c6f328SShengzhou Liu /**
2*48c6f328SShengzhou Liu * Copyright 2014 Freescale Semiconductor
3*48c6f328SShengzhou Liu *
4*48c6f328SShengzhou Liu * SPDX-License-Identifier: GPL-2.0+
5*48c6f328SShengzhou Liu *
6*48c6f328SShengzhou Liu * Freescale T1024RDB board-specific CPLD controlling supports.
7*48c6f328SShengzhou Liu *
8*48c6f328SShengzhou Liu * The following macros need to be defined:
9*48c6f328SShengzhou Liu */
10*48c6f328SShengzhou Liu
11*48c6f328SShengzhou Liu #include <common.h>
12*48c6f328SShengzhou Liu #include <command.h>
13*48c6f328SShengzhou Liu #include <asm/io.h>
14*48c6f328SShengzhou Liu #include "cpld.h"
15*48c6f328SShengzhou Liu
cpld_read(unsigned int reg)16*48c6f328SShengzhou Liu u8 cpld_read(unsigned int reg)
17*48c6f328SShengzhou Liu {
18*48c6f328SShengzhou Liu void *p = (void *)CONFIG_SYS_CPLD_BASE;
19*48c6f328SShengzhou Liu
20*48c6f328SShengzhou Liu return in_8(p + reg);
21*48c6f328SShengzhou Liu }
22*48c6f328SShengzhou Liu
cpld_write(unsigned int reg,u8 value)23*48c6f328SShengzhou Liu void cpld_write(unsigned int reg, u8 value)
24*48c6f328SShengzhou Liu {
25*48c6f328SShengzhou Liu void *p = (void *)CONFIG_SYS_CPLD_BASE;
26*48c6f328SShengzhou Liu
27*48c6f328SShengzhou Liu out_8(p + reg, value);
28*48c6f328SShengzhou Liu }
29*48c6f328SShengzhou Liu
30*48c6f328SShengzhou Liu /**
31*48c6f328SShengzhou Liu * Set the boot bank to the alternate bank
32*48c6f328SShengzhou Liu */
cpld_set_altbank(void)33*48c6f328SShengzhou Liu void cpld_set_altbank(void)
34*48c6f328SShengzhou Liu {
35*48c6f328SShengzhou Liu u8 reg = CPLD_READ(flash_csr);
36*48c6f328SShengzhou Liu
37*48c6f328SShengzhou Liu reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK;
38*48c6f328SShengzhou Liu
39*48c6f328SShengzhou Liu CPLD_WRITE(flash_csr, reg);
40*48c6f328SShengzhou Liu CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
41*48c6f328SShengzhou Liu }
42*48c6f328SShengzhou Liu
43*48c6f328SShengzhou Liu /**
44*48c6f328SShengzhou Liu * Set the boot bank to the default bank
45*48c6f328SShengzhou Liu */
cpld_set_defbank(void)46*48c6f328SShengzhou Liu void cpld_set_defbank(void)
47*48c6f328SShengzhou Liu {
48*48c6f328SShengzhou Liu u8 reg = CPLD_READ(flash_csr);
49*48c6f328SShengzhou Liu
50*48c6f328SShengzhou Liu reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK;
51*48c6f328SShengzhou Liu
52*48c6f328SShengzhou Liu CPLD_WRITE(flash_csr, reg);
53*48c6f328SShengzhou Liu CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
54*48c6f328SShengzhou Liu }
55*48c6f328SShengzhou Liu
cpld_dump_regs(void)56*48c6f328SShengzhou Liu static void cpld_dump_regs(void)
57*48c6f328SShengzhou Liu {
58*48c6f328SShengzhou Liu printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver));
59*48c6f328SShengzhou Liu printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub));
60*48c6f328SShengzhou Liu printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver));
61*48c6f328SShengzhou Liu printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver));
62*48c6f328SShengzhou Liu printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1));
63*48c6f328SShengzhou Liu printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2));
64*48c6f328SShengzhou Liu printf("int_status = 0x%02x\n", CPLD_READ(int_status));
65*48c6f328SShengzhou Liu printf("flash_csr = 0x%02x\n", CPLD_READ(flash_csr));
66*48c6f328SShengzhou Liu printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status));
67*48c6f328SShengzhou Liu printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status));
68*48c6f328SShengzhou Liu printf("sfp_ctl_status = 0x%02x\n", CPLD_READ(sfp_ctl_status));
69*48c6f328SShengzhou Liu printf("misc_ctl_status = 0x%02x\n", CPLD_READ(misc_ctl_status));
70*48c6f328SShengzhou Liu printf("boot_override = 0x%02x\n", CPLD_READ(boot_override));
71*48c6f328SShengzhou Liu printf("boot_config1 = 0x%02x\n", CPLD_READ(boot_config1));
72*48c6f328SShengzhou Liu printf("boot_config2 = 0x%02x\n", CPLD_READ(boot_config2));
73*48c6f328SShengzhou Liu putc('\n');
74*48c6f328SShengzhou Liu }
75*48c6f328SShengzhou Liu
do_cpld(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])76*48c6f328SShengzhou Liu int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
77*48c6f328SShengzhou Liu {
78*48c6f328SShengzhou Liu int rc = 0;
79*48c6f328SShengzhou Liu
80*48c6f328SShengzhou Liu if (argc <= 1)
81*48c6f328SShengzhou Liu return cmd_usage(cmdtp);
82*48c6f328SShengzhou Liu
83*48c6f328SShengzhou Liu if (strcmp(argv[1], "reset") == 0) {
84*48c6f328SShengzhou Liu if (strcmp(argv[2], "altbank") == 0)
85*48c6f328SShengzhou Liu cpld_set_altbank();
86*48c6f328SShengzhou Liu else
87*48c6f328SShengzhou Liu cpld_set_defbank();
88*48c6f328SShengzhou Liu } else if (strcmp(argv[1], "dump") == 0) {
89*48c6f328SShengzhou Liu cpld_dump_regs();
90*48c6f328SShengzhou Liu } else {
91*48c6f328SShengzhou Liu rc = cmd_usage(cmdtp);
92*48c6f328SShengzhou Liu }
93*48c6f328SShengzhou Liu
94*48c6f328SShengzhou Liu return rc;
95*48c6f328SShengzhou Liu }
96*48c6f328SShengzhou Liu
97*48c6f328SShengzhou Liu U_BOOT_CMD(
98*48c6f328SShengzhou Liu cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
99*48c6f328SShengzhou Liu "Reset the board or alternate bank",
100*48c6f328SShengzhou Liu "reset - hard reset to default bank\n"
101*48c6f328SShengzhou Liu "cpld reset altbank - reset to alternate bank\n"
102*48c6f328SShengzhou Liu "cpld dump - display the CPLD registers\n"
103*48c6f328SShengzhou Liu );
104