1*4f1d1b7dSMingkai Hu /** 2*4f1d1b7dSMingkai Hu * Copyright 2011 Freescale Semiconductor 3*4f1d1b7dSMingkai Hu * Author: Mingkai Hu <Mingkai.hu@freescale.com> 4*4f1d1b7dSMingkai Hu * 5*4f1d1b7dSMingkai Hu * This program is free software; you can redistribute it and/or modify it 6*4f1d1b7dSMingkai Hu * under the terms of the GNU General Public License as published by the Free 7*4f1d1b7dSMingkai Hu * Software Foundation; either version 2 of the License, or (at your option) 8*4f1d1b7dSMingkai Hu * any later version. 9*4f1d1b7dSMingkai Hu * 10*4f1d1b7dSMingkai Hu * This file provides support for the ngPIXIS, a board-specific FPGA used on 11*4f1d1b7dSMingkai Hu * some Freescale reference boards. 12*4f1d1b7dSMingkai Hu */ 13*4f1d1b7dSMingkai Hu 14*4f1d1b7dSMingkai Hu /* 15*4f1d1b7dSMingkai Hu * CPLD register set. Feel free to add board-specific #ifdefs where necessary. 16*4f1d1b7dSMingkai Hu */ 17*4f1d1b7dSMingkai Hu typedef struct cpld_data { 18*4f1d1b7dSMingkai Hu u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */ 19*4f1d1b7dSMingkai Hu u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */ 20*4f1d1b7dSMingkai Hu u8 pcba_ver; /* 0x2 - PCBA Revision Register */ 21*4f1d1b7dSMingkai Hu u8 system_rst; /* 0x3 - system reset register */ 22*4f1d1b7dSMingkai Hu u8 wd_cfg; /* 0x4 - Watchdog Period Setting Register */ 23*4f1d1b7dSMingkai Hu u8 sw_ctl_on; /* 0x5 - Switch Control Enable Register */ 24*4f1d1b7dSMingkai Hu u8 por_cfg; /* 0x6 - POR Control Register */ 25*4f1d1b7dSMingkai Hu u8 switch_strobe; /* 0x7 - Multiplexed pin Select Register */ 26*4f1d1b7dSMingkai Hu u8 jtag_sel; /* 0x8 - JTAG or AURORA Selection */ 27*4f1d1b7dSMingkai Hu u8 sdbank1_clk; /* 0x9 - SerDes Bank1 Reference clock */ 28*4f1d1b7dSMingkai Hu u8 sdbank2_clk; /* 0xa - SerDes Bank2 Reference clock */ 29*4f1d1b7dSMingkai Hu u8 fbank_sel; /* 0xb - Flash bank selection */ 30*4f1d1b7dSMingkai Hu u8 serdes_mux; /* 0xc - Multiplexed pin Select Register */ 31*4f1d1b7dSMingkai Hu u8 sw[1]; /* 0xd - SW2 Status */ 32*4f1d1b7dSMingkai Hu } __attribute__ ((packed)) cpld_data_t; 33*4f1d1b7dSMingkai Hu 34*4f1d1b7dSMingkai Hu #define SERDES_MUX_LANE_6_MASK 0x2 35*4f1d1b7dSMingkai Hu #define SERDES_MUX_LANE_6_SHIFT 1 36*4f1d1b7dSMingkai Hu #define SERDES_MUX_LANE_A_MASK 0x1 37*4f1d1b7dSMingkai Hu #define SERDES_MUX_LANE_A_SHIFT 0 38*4f1d1b7dSMingkai Hu #define SERDES_MUX_LANE_C_MASK 0x4 39*4f1d1b7dSMingkai Hu #define SERDES_MUX_LANE_C_SHIFT 2 40*4f1d1b7dSMingkai Hu #define SERDES_MUX_LANE_D_MASK 0x8 41*4f1d1b7dSMingkai Hu #define SERDES_MUX_LANE_D_SHIFT 3 42*4f1d1b7dSMingkai Hu 43*4f1d1b7dSMingkai Hu /* Pointer to the CPLD register set */ 44*4f1d1b7dSMingkai Hu #define cpld ((cpld_data_t *)CPLD_BASE) 45*4f1d1b7dSMingkai Hu 46*4f1d1b7dSMingkai Hu /* The CPLD SW register that corresponds to board switch X, where x >= 1 */ 47*4f1d1b7dSMingkai Hu #define CPLD_SW(x) (cpld->sw[(x) - 2]) 48*4f1d1b7dSMingkai Hu 49*4f1d1b7dSMingkai Hu u8 cpld_read(unsigned int reg); 50*4f1d1b7dSMingkai Hu void cpld_write(unsigned int reg, u8 value); 51*4f1d1b7dSMingkai Hu 52*4f1d1b7dSMingkai Hu #define CPLD_READ(reg) cpld_read(offsetof(cpld_data_t, reg)) 53*4f1d1b7dSMingkai Hu #define CPLD_WRITE(reg, value) cpld_write(offsetof(cpld_data_t, reg), value) 54