1 /** 2 * Copyright 2011 Freescale Semiconductor 3 * Author: Mingkai Hu <Mingkai.hu@freescale.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the Free 7 * Software Foundation; either version 2 of the License, or (at your option) 8 * any later version. 9 * 10 * This file provides support for the board-specific CPLD used on some Freescale 11 * reference boards. 12 * 13 * The following macros need to be defined: 14 * 15 * CPLD_BASE - The virtual address of the base of the CPLD register map 16 * 17 */ 18 19 #include <common.h> 20 #include <command.h> 21 #include <asm/io.h> 22 23 #include "cpld.h" 24 25 static u8 __cpld_read(unsigned int reg) 26 { 27 void *p = (void *)CPLD_BASE; 28 29 return in_8(p + reg); 30 } 31 u8 cpld_read(unsigned int reg) __attribute__((weak, alias("__cpld_read"))); 32 33 static void __cpld_write(unsigned int reg, u8 value) 34 { 35 void *p = (void *)CPLD_BASE; 36 37 out_8(p + reg, value); 38 } 39 void cpld_write(unsigned int reg, u8 value) 40 __attribute__((weak, alias("__cpld_write"))); 41 42 /* 43 * Reset the board. This honors the por_cfg registers. 44 */ 45 void __cpld_reset(void) 46 { 47 CPLD_WRITE(system_rst, 1); 48 } 49 void cpld_reset(void) __attribute__((weak, alias("__cpld_reset"))); 50 51 /** 52 * Set the boot bank to the alternate bank 53 */ 54 void __cpld_set_altbank(void) 55 { 56 u8 reg5 = CPLD_READ(sw_ctl_on); 57 58 CPLD_WRITE(sw_ctl_on, reg5 | CPLD_SWITCH_BANK_ENABLE); 59 CPLD_WRITE(fbank_sel, 1); 60 CPLD_WRITE(system_rst, 1); 61 } 62 void cpld_set_altbank(void) 63 __attribute__((weak, alias("__cpld_set_altbank"))); 64 65 /** 66 * Set the boot bank to the default bank 67 */ 68 void __cpld_set_defbank(void) 69 { 70 CPLD_WRITE(system_rst_default, 1); 71 } 72 void cpld_set_defbank(void) 73 __attribute__((weak, alias("__cpld_set_defbank"))); 74 75 #ifdef DEBUG 76 static void cpld_dump_regs(void) 77 { 78 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); 79 printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); 80 printf("pcba_ver = 0x%02x\n", CPLD_READ(pcba_ver)); 81 printf("system_rst = 0x%02x\n", CPLD_READ(system_rst)); 82 printf("wd_cfg = 0x%02x\n", CPLD_READ(wd_cfg)); 83 printf("sw_ctl_on = 0x%02x\n", CPLD_READ(sw_ctl_on)); 84 printf("por_cfg = 0x%02x\n", CPLD_READ(por_cfg)); 85 printf("switch_strobe = 0x%02x\n", CPLD_READ(switch_strobe)); 86 printf("jtag_sel = 0x%02x\n", CPLD_READ(jtag_sel)); 87 printf("sdbank1_clk = 0x%02x\n", CPLD_READ(sdbank1_clk)); 88 printf("sdbank2_clk = 0x%02x\n", CPLD_READ(sdbank2_clk)); 89 printf("fbank_sel = 0x%02x\n", CPLD_READ(fbank_sel)); 90 printf("serdes_mux = 0x%02x\n", CPLD_READ(serdes_mux)); 91 printf("SW[2] = 0x%02x\n", in_8(&CPLD_SW(2))); 92 putc('\n'); 93 } 94 #endif 95 96 int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 97 { 98 int rc = 0; 99 unsigned int i; 100 101 if (argc <= 1) 102 return cmd_usage(cmdtp); 103 104 if (strcmp(argv[1], "reset") == 0) { 105 if (strcmp(argv[2], "altbank") == 0) 106 cpld_set_altbank(); 107 else 108 cpld_set_defbank(); 109 } else if (strcmp(argv[1], "watchdog") == 0) { 110 static char *period[8] = {"1ms", "10ms", "30ms", "disable", 111 "100ms", "1s", "10s", "60s"}; 112 for (i = 0; i < ARRAY_SIZE(period); i++) { 113 if (strcmp(argv[2], period[i]) == 0) 114 CPLD_WRITE(wd_cfg, i); 115 } 116 } else if (strcmp(argv[1], "lane_mux") == 0) { 117 u32 lane = simple_strtoul(argv[2], NULL, 16); 118 u8 val = (u8)simple_strtoul(argv[3], NULL, 16); 119 u8 reg = CPLD_READ(serdes_mux); 120 121 switch (lane) { 122 case 0x6: 123 reg &= ~SERDES_MUX_LANE_6_MASK; 124 reg |= val << SERDES_MUX_LANE_6_SHIFT; 125 break; 126 case 0xa: 127 reg &= ~SERDES_MUX_LANE_A_MASK; 128 reg |= val << SERDES_MUX_LANE_A_SHIFT; 129 break; 130 case 0xc: 131 reg &= ~SERDES_MUX_LANE_C_MASK; 132 reg |= val << SERDES_MUX_LANE_C_SHIFT; 133 break; 134 case 0xd: 135 reg &= ~SERDES_MUX_LANE_D_MASK; 136 reg |= val << SERDES_MUX_LANE_D_SHIFT; 137 break; 138 default: 139 printf("Invalid value\n"); 140 break; 141 } 142 143 CPLD_WRITE(serdes_mux, reg); 144 #ifdef DEBUG 145 } else if (strcmp(argv[1], "dump") == 0) { 146 cpld_dump_regs(); 147 #endif 148 } else 149 rc = cmd_usage(cmdtp); 150 151 return rc; 152 } 153 154 U_BOOT_CMD( 155 cpld_cmd, CONFIG_SYS_MAXARGS, 1, cpld_cmd, 156 "Reset the board or pin mulexing selection using the CPLD sequencer", 157 "reset - hard reset to default bank\n" 158 "cpld_cmd reset altbank - reset to alternate bank\n" 159 "cpld_cmd watchdog <watchdog_period> - set the watchdog period\n" 160 " period: 1ms 10ms 30ms 100ms 1s 10s 60s disable\n" 161 "cpld_cmd lane_mux <lane> <mux_value> - set multiplexed lane pin\n" 162 " lane 6: 0 -> slot1\n" 163 " 1 -> SGMII (Default)\n" 164 " lane a: 0 -> slot2\n" 165 " 1 -> AURORA (Default)\n" 166 " lane c: 0 -> slot2\n" 167 " 1 -> SATA0 (Default)\n" 168 " lane d: 0 -> slot2\n" 169 " 1 -> SATA1 (Default)\n" 170 #ifdef DEBUG 171 "cpld_cmd dump - display the CPLD registers\n" 172 #endif 173 ); 174