1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/processor.h> 9 #include <asm/mmu.h> 10 #include <asm/cache.h> 11 #include <asm/immap_85xx.h> 12 #include <asm/io.h> 13 #include <miiphy.h> 14 #include <libfdt.h> 15 #include <fdt_support.h> 16 #include <fsl_mdio.h> 17 #include <tsec.h> 18 #include <mmc.h> 19 #include <netdev.h> 20 #include <pci.h> 21 #include <asm/fsl_serdes.h> 22 #include <asm/fsl_ifc.h> 23 #include <asm/fsl_pci.h> 24 25 #ifndef CONFIG_SDCARD 26 #include <hwconfig.h> 27 #endif 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 #define GPIO4_PCIE_RESET_SET 0x08000000 32 #define MUX_CPLD_CAN_UART 0x00 33 #define MUX_CPLD_TDM 0x01 34 #define MUX_CPLD_SPICS0_FLASH 0x00 35 #define MUX_CPLD_SPICS0_SLIC 0x02 36 37 #ifndef CONFIG_SDCARD 38 struct cpld_data { 39 u8 cpld_ver; /* cpld revision */ 40 u8 pcba_ver; /* pcb revision number */ 41 u8 twindie_ddr3; 42 u8 res1[6]; 43 u8 bank_sel; /* NOR Flash bank */ 44 u8 res2[5]; 45 u8 usb2_sel; 46 u8 res3[1]; 47 u8 porsw_sel; 48 u8 tdm_can_sel; 49 u8 spi_cs0_sel; /* SPI CS0 SLIC/SPI Flash */ 50 u8 por0; /* POR Options */ 51 u8 por1; /* POR Options */ 52 u8 por2; /* POR Options */ 53 u8 por3; /* POR Options */ 54 }; 55 #endif 56 57 int board_early_init_f(void) 58 { 59 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); 60 #ifndef CONFIG_SDCARD 61 struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR; 62 63 /* Clock configuration to access CPLD using IFC(GPCM) */ 64 setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); 65 #endif 66 /* 67 * Reset PCIe slots via GPIO4 68 */ 69 setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET); 70 setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET); 71 72 return 0; 73 } 74 75 int board_early_init_r(void) 76 { 77 #ifndef CONFIG_SDCARD 78 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 79 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 80 81 /* 82 * Remap Boot flash region to caching-inhibited 83 * so that flash can be erased properly. 84 */ 85 86 /* Flush d-cache and invalidate i-cache of any FLASH data */ 87 flush_dcache(); 88 invalidate_icache(); 89 90 /* invalidate existing TLB entry for flash */ 91 disable_tlb(flash_esel); 92 93 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, 94 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 95 0, flash_esel, BOOKE_PAGESZ_16M, 1); 96 97 set_tlb(1, flashbase + 0x1000000, 98 CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000, 99 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 100 0, flash_esel+1, BOOKE_PAGESZ_16M, 1); 101 #endif 102 return 0; 103 } 104 105 #ifdef CONFIG_PCI 106 void pci_init_board(void) 107 { 108 fsl_pcie_init_board(0); 109 } 110 #endif /* ifdef CONFIG_PCI */ 111 112 int checkboard(void) 113 { 114 struct cpu_type *cpu; 115 116 cpu = gd->arch.cpu; 117 printf("Board: %sRDB\n", cpu->name); 118 119 return 0; 120 } 121 122 #ifdef CONFIG_TSEC_ENET 123 int board_eth_init(bd_t *bis) 124 { 125 struct fsl_pq_mdio_info mdio_info; 126 struct tsec_info_struct tsec_info[4]; 127 struct cpu_type *cpu; 128 int num = 0; 129 130 cpu = gd->arch.cpu; 131 132 #ifdef CONFIG_TSEC1 133 SET_STD_TSEC_INFO(tsec_info[num], 1); 134 num++; 135 #endif 136 #ifdef CONFIG_TSEC2 137 SET_STD_TSEC_INFO(tsec_info[num], 2); 138 num++; 139 #endif 140 #ifdef CONFIG_TSEC3 141 /* P1014 and it's derivatives do not support eTSEC3 */ 142 if (cpu->soc_ver != SVR_P1014) { 143 SET_STD_TSEC_INFO(tsec_info[num], 3); 144 num++; 145 } 146 #endif 147 if (!num) { 148 printf("No TSECs initialized\n"); 149 return 0; 150 } 151 152 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; 153 mdio_info.name = DEFAULT_MII_NAME; 154 155 fsl_pq_mdio_init(bis, &mdio_info); 156 157 tsec_eth_init(bis, tsec_info, num); 158 159 return pci_eth_init(bis); 160 } 161 #endif 162 163 #if defined(CONFIG_OF_BOARD_SETUP) 164 void fdt_del_flexcan(void *blob) 165 { 166 int nodeoff = 0; 167 168 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, 169 "fsl,p1010-flexcan")) >= 0) { 170 fdt_del_node(blob, nodeoff); 171 } 172 } 173 174 void fdt_del_spi_flash(void *blob) 175 { 176 int nodeoff = 0; 177 178 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, 179 "spansion,s25sl12801")) >= 0) { 180 fdt_del_node(blob, nodeoff); 181 } 182 } 183 184 void fdt_del_spi_slic(void *blob) 185 { 186 int nodeoff = 0; 187 188 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, 189 "zarlink,le88266")) >= 0) { 190 fdt_del_node(blob, nodeoff); 191 } 192 } 193 194 void fdt_del_tdm(void *blob) 195 { 196 int nodeoff = 0; 197 198 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, 199 "fsl,starlite-tdm")) >= 0) { 200 fdt_del_node(blob, nodeoff); 201 } 202 } 203 204 void fdt_del_sdhc(void *blob) 205 { 206 int nodeoff = 0; 207 208 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, 209 "fsl,esdhc")) >= 0) { 210 fdt_del_node(blob, nodeoff); 211 } 212 } 213 214 void fdt_disable_uart1(void *blob) 215 { 216 int nodeoff; 217 218 nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550", 219 CONFIG_SYS_NS16550_COM2); 220 221 if (nodeoff > 0) { 222 fdt_status_disabled(blob, nodeoff); 223 } else { 224 printf("WARNING unable to set status for fsl,ns16550 " 225 "uart1: %s\n", fdt_strerror(nodeoff)); 226 } 227 } 228 229 void ft_board_setup(void *blob, bd_t *bd) 230 { 231 phys_addr_t base; 232 phys_size_t size; 233 struct cpu_type *cpu; 234 235 cpu = gd->arch.cpu; 236 237 ft_cpu_setup(blob, bd); 238 239 base = getenv_bootm_low(); 240 size = getenv_bootm_size(); 241 242 #if defined(CONFIG_PCI) 243 FT_FSL_PCI_SETUP; 244 #endif 245 246 fdt_fixup_memory(blob, (u64)base, (u64)size); 247 248 #if defined(CONFIG_HAS_FSL_DR_USB) 249 fdt_fixup_dr_usb(blob, bd); 250 #endif 251 252 /* P1014 and it's derivatives don't support CAN and eTSEC3 */ 253 if (cpu->soc_ver == SVR_P1014) { 254 fdt_del_flexcan(blob); 255 fdt_del_node_and_alias(blob, "ethernet2"); 256 } 257 #ifndef CONFIG_SDCARD 258 /* disable sdhc due to sdhc bug */ 259 fdt_del_sdhc(blob); 260 if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) { 261 fdt_del_tdm(blob); 262 fdt_del_spi_slic(blob); 263 } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) { 264 fdt_del_flexcan(blob); 265 fdt_del_spi_flash(blob); 266 fdt_disable_uart1(blob); 267 } else { 268 /* 269 * If we don't set fsl_p1010mux:tdm_can to "can" or "tdm" 270 * explicitly, defaultly spi_cs_sel to spi-flash instead of 271 * to tdm/slic. 272 */ 273 fdt_del_tdm(blob); 274 fdt_del_flexcan(blob); 275 fdt_disable_uart1(blob); 276 } 277 #endif 278 } 279 #endif 280 281 #ifndef CONFIG_SDCARD 282 int misc_init_r(void) 283 { 284 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 285 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 286 287 if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) { 288 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM | 289 MPC85xx_PMUXCR_CAN1_UART | 290 MPC85xx_PMUXCR_CAN2_TDM | 291 MPC85xx_PMUXCR_CAN2_UART); 292 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART); 293 } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) { 294 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART | 295 MPC85xx_PMUXCR_CAN1_UART); 296 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM | 297 MPC85xx_PMUXCR_CAN1_TDM); 298 clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO); 299 setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM); 300 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM); 301 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC); 302 } else { 303 /* defaultly spi_cs_sel to flash */ 304 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH); 305 } 306 307 return 0; 308 } 309 #endif 310