1 /* 2 * Copyright (C) 2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <asm/arch/clock.h> 8 #include <asm/arch/imx-regs.h> 9 #include <asm/arch/mx7-pins.h> 10 #include <asm/arch/sys_proto.h> 11 #include <asm/gpio.h> 12 #include <asm/imx-common/iomux-v3.h> 13 #include <asm/io.h> 14 #include <linux/sizes.h> 15 #include <common.h> 16 #include <fsl_esdhc.h> 17 #include <mmc.h> 18 #include <miiphy.h> 19 #include <netdev.h> 20 #include <power/pmic.h> 21 #include <power/pfuze3000_pmic.h> 22 #include "../common/pfuze.h" 23 #include <i2c.h> 24 #include <asm/imx-common/mxc_i2c.h> 25 #include <asm/arch/crm_regs.h> 26 #include <usb.h> 27 #include <usb/ehci-ci.h> 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ 32 PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) 33 34 #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) 35 #define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM) 36 37 #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) 38 39 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ 40 PAD_CTL_DSE_3P3V_49OHM) 41 42 #define QSPI_PAD_CTRL \ 43 (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) 44 45 #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) 46 47 #define SPI_PAD_CTRL \ 48 (PAD_CTL_HYS | PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST) 49 50 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM) 51 52 #ifdef CONFIG_MXC_SPI 53 static iomux_v3_cfg_t const ecspi3_pads[] = { 54 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), 55 MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), 56 MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), 57 MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), 58 }; 59 60 int board_spi_cs_gpio(unsigned bus, unsigned cs) 61 { 62 return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(6, 22)) : -1; 63 } 64 65 static void setup_spi(void) 66 { 67 imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads)); 68 } 69 #endif 70 71 int dram_init(void) 72 { 73 gd->ram_size = PHYS_SDRAM_SIZE; 74 75 return 0; 76 } 77 78 static iomux_v3_cfg_t const wdog_pads[] = { 79 MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), 80 }; 81 82 static iomux_v3_cfg_t const uart1_pads[] = { 83 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 84 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 85 }; 86 87 static iomux_v3_cfg_t const usb_otg1_pads[] = { 88 MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 89 }; 90 91 static iomux_v3_cfg_t const usb_otg2_pads[] = { 92 MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 93 }; 94 95 #ifdef CONFIG_NAND_MXS 96 static iomux_v3_cfg_t const gpmi_pads[] = { 97 MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), 98 MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), 99 MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), 100 MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), 101 MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), 102 MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), 103 MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), 104 MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), 105 MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), 106 MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), 107 MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 108 MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 109 MX7D_PAD_SAI1_MCLK__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 110 MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 111 MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 112 MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 113 MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 114 MX7D_PAD_SAI1_TX_SYNC__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL), 115 MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), 116 }; 117 118 static void setup_gpmi_nand(void) 119 { 120 imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); 121 122 /* NAND_USDHC_BUS_CLK is set in rom */ 123 set_clk_nand(); 124 } 125 #endif 126 127 #ifdef CONFIG_VIDEO_MXS 128 static iomux_v3_cfg_t const lcd_pads[] = { 129 MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), 130 MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), 131 MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 132 MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 133 MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL), 134 MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL), 135 MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL), 136 MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL), 137 MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL), 138 MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL), 139 MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL), 140 MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL), 141 MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL), 142 MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL), 143 MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), 144 MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), 145 MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), 146 MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), 147 MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), 148 MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), 149 MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), 150 MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), 151 MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), 152 MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), 153 MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), 154 MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), 155 MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), 156 MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), 157 158 MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL), 159 }; 160 161 static iomux_v3_cfg_t const pwm_pads[] = { 162 /* Use GPIO for Brightness adjustment, duty cycle = period */ 163 MX7D_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL), 164 }; 165 166 static int setup_lcd(void) 167 { 168 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); 169 170 imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads)); 171 172 /* Reset LCD */ 173 gpio_request(IMX_GPIO_NR(3, 4), "lcd reset"); 174 gpio_direction_output(IMX_GPIO_NR(3, 4) , 0); 175 udelay(500); 176 gpio_direction_output(IMX_GPIO_NR(3, 4) , 1); 177 178 /* Set Brightness to high */ 179 gpio_request(IMX_GPIO_NR(1, 1), "lcd backlight"); 180 gpio_direction_output(IMX_GPIO_NR(1, 1) , 1); 181 182 return 0; 183 } 184 #endif 185 186 #ifdef CONFIG_FEC_MXC 187 static iomux_v3_cfg_t const fec1_pads[] = { 188 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 189 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 190 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 191 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 192 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 193 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 194 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 195 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 196 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 197 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 198 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 199 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 200 MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), 201 MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), 202 }; 203 204 static void setup_iomux_fec(void) 205 { 206 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); 207 } 208 #endif 209 210 static void setup_iomux_uart(void) 211 { 212 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 213 } 214 215 int board_mmc_get_env_dev(int devno) 216 { 217 if (devno == 2) 218 devno--; 219 220 return devno; 221 } 222 223 int mmc_map_to_kernel_blk(int dev_no) 224 { 225 if (dev_no == 1) 226 dev_no++; 227 228 return dev_no; 229 } 230 231 #ifdef CONFIG_FEC_MXC 232 int board_eth_init(bd_t *bis) 233 { 234 int ret; 235 236 setup_iomux_fec(); 237 238 ret = fecmxc_initialize_multi(bis, 0, 239 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); 240 if (ret) 241 printf("FEC1 MXC: %s:failed\n", __func__); 242 243 return ret; 244 } 245 246 static int setup_fec(void) 247 { 248 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs 249 = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; 250 251 /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ 252 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], 253 (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK | 254 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0); 255 256 return set_clk_enet(ENET_125MHz); 257 } 258 259 260 int board_phy_config(struct phy_device *phydev) 261 { 262 /* enable rgmii rxc skew and phy mode select to RGMII copper */ 263 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21); 264 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8); 265 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f); 266 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7); 267 268 if (phydev->drv->config) 269 phydev->drv->config(phydev); 270 return 0; 271 } 272 #endif 273 274 #ifdef CONFIG_FSL_QSPI 275 static iomux_v3_cfg_t const quadspi_pads[] = { 276 MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), 277 MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), 278 MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), 279 MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), 280 MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), 281 MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), 282 }; 283 284 int board_qspi_init(void) 285 { 286 /* Set the iomux */ 287 imx_iomux_v3_setup_multiple_pads(quadspi_pads, 288 ARRAY_SIZE(quadspi_pads)); 289 290 /* Set the clock */ 291 set_clk_qspi(); 292 293 return 0; 294 } 295 #endif 296 297 int board_early_init_f(void) 298 { 299 setup_iomux_uart(); 300 301 imx_iomux_v3_setup_multiple_pads(usb_otg1_pads, 302 ARRAY_SIZE(usb_otg1_pads)); 303 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, 304 ARRAY_SIZE(usb_otg2_pads)); 305 306 return 0; 307 } 308 309 int board_init(void) 310 { 311 /* address of boot parameters */ 312 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 313 314 #ifdef CONFIG_FEC_MXC 315 setup_fec(); 316 #endif 317 318 #ifdef CONFIG_NAND_MXS 319 setup_gpmi_nand(); 320 #endif 321 322 #ifdef CONFIG_VIDEO_MXS 323 setup_lcd(); 324 #endif 325 326 #ifdef CONFIG_FSL_QSPI 327 board_qspi_init(); 328 #endif 329 330 #ifdef CONFIG_MXC_SPI 331 setup_spi(); 332 #endif 333 334 return 0; 335 } 336 337 #ifdef CONFIG_DM_PMIC 338 int power_init_board(void) 339 { 340 struct udevice *dev; 341 int ret, dev_id, rev_id; 342 343 ret = pmic_get("pfuze3000", &dev); 344 if (ret == -ENODEV) 345 return 0; 346 if (ret != 0) 347 return ret; 348 349 dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID); 350 rev_id = pmic_reg_read(dev, PFUZE3000_REVID); 351 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); 352 353 pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1); 354 355 return 0; 356 } 357 #endif 358 359 int board_late_init(void) 360 { 361 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; 362 363 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); 364 365 set_wdog_reset(wdog); 366 367 /* 368 * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4), 369 * since we use PMIC_PWRON to reset the board. 370 */ 371 clrsetbits_le16(&wdog->wcr, 0, 0x10); 372 373 return 0; 374 } 375 376 int checkboard(void) 377 { 378 char *mode; 379 380 if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT)) 381 mode = "secure"; 382 else 383 mode = "non-secure"; 384 385 printf("Board: i.MX7D SABRESD in %s mode\n", mode); 386 387 return 0; 388 } 389 390 #ifdef CONFIG_USB_EHCI_MX7 391 int board_usb_phy_mode(int port) 392 { 393 if (port == 0) 394 return USB_INIT_DEVICE; 395 else 396 return USB_INIT_HOST; 397 } 398 #endif 399