114a16131SFabio Estevam/* 214a16131SFabio Estevam * Copyright (C) 2014 Freescale Semiconductor, Inc. 314a16131SFabio Estevam * 414a16131SFabio Estevam * SPDX-License-Identifier: GPL-2.0+ 514a16131SFabio Estevam */ 614a16131SFabio Estevam 714a16131SFabio Estevam#define __ASSEMBLY__ 814a16131SFabio Estevam#include <config.h> 914a16131SFabio Estevam 1014a16131SFabio Estevam/* image version */ 1114a16131SFabio Estevam 1214a16131SFabio EstevamIMAGE_VERSION 2 1314a16131SFabio Estevam 1414a16131SFabio Estevam/* 1514a16131SFabio Estevam * Boot Device : one of 1614a16131SFabio Estevam * spi/sd/nand/onenand, qspi/nor 1714a16131SFabio Estevam */ 1814a16131SFabio Estevam 1914a16131SFabio EstevamBOOT_FROM sd 2014a16131SFabio Estevam 2114a16131SFabio Estevam/* 2214a16131SFabio Estevam * Device Configuration Data (DCD) 2314a16131SFabio Estevam * 2414a16131SFabio Estevam * Each entry must have the format: 2514a16131SFabio Estevam * Addr-type Address Value 2614a16131SFabio Estevam * 2714a16131SFabio Estevam * where: 2814a16131SFabio Estevam * Addr-type register length (1,2 or 4 bytes) 2914a16131SFabio Estevam * Address absolute address of the register 3014a16131SFabio Estevam * value value to be stored in the register 3114a16131SFabio Estevam */ 3214a16131SFabio Estevam 33*eb5c1807SFabio Estevam/* Enable all clocks */ 3414a16131SFabio EstevamDATA 4 0x020c4068 0xffffffff 3514a16131SFabio EstevamDATA 4 0x020c406c 0xffffffff 3614a16131SFabio EstevamDATA 4 0x020c4070 0xffffffff 3714a16131SFabio EstevamDATA 4 0x020c4074 0xffffffff 3814a16131SFabio EstevamDATA 4 0x020c4078 0xffffffff 3914a16131SFabio EstevamDATA 4 0x020c407c 0xffffffff 4014a16131SFabio EstevamDATA 4 0x020c4080 0xffffffff 4114a16131SFabio EstevamDATA 4 0x020c4084 0xffffffff 4214a16131SFabio Estevam 43*eb5c1807SFabio Estevam/* IOMUX - DDR IO Type */ 4414a16131SFabio EstevamDATA 4 0x020e0618 0x000c0000 4514a16131SFabio EstevamDATA 4 0x020e05fc 0x00000000 46*eb5c1807SFabio Estevam 47*eb5c1807SFabio Estevam/* Clock */ 4814a16131SFabio EstevamDATA 4 0x020e032c 0x00000030 4914a16131SFabio Estevam 50*eb5c1807SFabio Estevam/* Address */ 51*eb5c1807SFabio EstevamDATA 4 0x020e0300 0x00000020 52*eb5c1807SFabio EstevamDATA 4 0x020e02fc 0x00000020 53*eb5c1807SFabio EstevamDATA 4 0x020e05f4 0x00000020 54*eb5c1807SFabio Estevam 55*eb5c1807SFabio Estevam/* Control */ 56*eb5c1807SFabio EstevamDATA 4 0x020e0340 0x00000020 5714a16131SFabio Estevam 5814a16131SFabio EstevamDATA 4 0x020e0320 0x00000000 59*eb5c1807SFabio EstevamDATA 4 0x020e0310 0x00000020 60*eb5c1807SFabio EstevamDATA 4 0x020e0314 0x00000020 61*eb5c1807SFabio EstevamDATA 4 0x020e0614 0x00000020 6214a16131SFabio Estevam 63*eb5c1807SFabio Estevam/* Data Strobe */ 6414a16131SFabio EstevamDATA 4 0x020e05f8 0x00020000 65*eb5c1807SFabio EstevamDATA 4 0x020e0330 0x00000028 66*eb5c1807SFabio EstevamDATA 4 0x020e0334 0x00000028 67*eb5c1807SFabio EstevamDATA 4 0x020e0338 0x00000028 68*eb5c1807SFabio EstevamDATA 4 0x020e033c 0x00000028 69*eb5c1807SFabio Estevam 70*eb5c1807SFabio Estevam/* Data */ 7114a16131SFabio EstevamDATA 4 0x020e0608 0x00020000 72*eb5c1807SFabio EstevamDATA 4 0x020e060c 0x00000028 73*eb5c1807SFabio EstevamDATA 4 0x020e0610 0x00000028 74*eb5c1807SFabio EstevamDATA 4 0x020e061c 0x00000028 75*eb5c1807SFabio EstevamDATA 4 0x020e0620 0x00000028 76*eb5c1807SFabio EstevamDATA 4 0x020e02ec 0x00000028 77*eb5c1807SFabio EstevamDATA 4 0x020e02f0 0x00000028 78*eb5c1807SFabio EstevamDATA 4 0x020e02f4 0x00000028 79*eb5c1807SFabio EstevamDATA 4 0x020e02f8 0x00000028 80*eb5c1807SFabio Estevam 81*eb5c1807SFabio Estevam/* Calibrations - ZQ */ 8214a16131SFabio EstevamDATA 4 0x021b0800 0xa1390003 83*eb5c1807SFabio Estevam 84*eb5c1807SFabio Estevam/* Write leveling */ 85*eb5c1807SFabio EstevamDATA 4 0x021b080c 0x00290025 86*eb5c1807SFabio EstevamDATA 4 0x021b0810 0x00220022 87*eb5c1807SFabio Estevam 88*eb5c1807SFabio Estevam/* DQS Read Gate */ 89*eb5c1807SFabio EstevamDATA 4 0x021b083c 0x41480144 90*eb5c1807SFabio EstevamDATA 4 0x021b0840 0x01340130 91*eb5c1807SFabio Estevam 92*eb5c1807SFabio Estevam/* Read/Write Delay */ 93*eb5c1807SFabio EstevamDATA 4 0x021b0848 0x3C3E4244 94*eb5c1807SFabio EstevamDATA 4 0x021b0850 0x34363638 95*eb5c1807SFabio Estevam 96*eb5c1807SFabio Estevam/* Read data bit delay */ 9714a16131SFabio EstevamDATA 4 0x021b081c 0x33333333 9814a16131SFabio EstevamDATA 4 0x021b0820 0x33333333 9914a16131SFabio EstevamDATA 4 0x021b0824 0x33333333 10014a16131SFabio EstevamDATA 4 0x021b0828 0x33333333 101*eb5c1807SFabio Estevam 102*eb5c1807SFabio Estevam/* Complete calibration by forced measurement */ 10314a16131SFabio EstevamDATA 4 0x021b08b8 0x00000800 104*eb5c1807SFabio Estevam 105*eb5c1807SFabio Estevam/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */ 10614a16131SFabio EstevamDATA 4 0x021b0004 0x0002002d 10714a16131SFabio EstevamDATA 4 0x021b0008 0x00333030 10814a16131SFabio EstevamDATA 4 0x021b000c 0x676b52f3 10914a16131SFabio EstevamDATA 4 0x021b0010 0xb66d8b63 11014a16131SFabio EstevamDATA 4 0x021b0014 0x01ff00db 11114a16131SFabio EstevamDATA 4 0x021b0018 0x00011740 11214a16131SFabio EstevamDATA 4 0x021b001c 0x00008000 11314a16131SFabio EstevamDATA 4 0x021b002c 0x000026d2 11414a16131SFabio EstevamDATA 4 0x021b0030 0x006b1023 11514a16131SFabio EstevamDATA 4 0x021b0040 0x0000005f 11614a16131SFabio EstevamDATA 4 0x021b0000 0x84190000 117*eb5c1807SFabio Estevam 118*eb5c1807SFabio Estevam/* Initialize MT41K256M16HA-125 - MR2 */ 11914a16131SFabio EstevamDATA 4 0x021b001c 0x04008032 120*eb5c1807SFabio Estevam/* MR3 */ 12114a16131SFabio EstevamDATA 4 0x021b001c 0x00008033 122*eb5c1807SFabio Estevam/* MR1 */ 123*eb5c1807SFabio EstevamDATA 4 0x021b001c 0x00048031 124*eb5c1807SFabio Estevam/* MR0 */ 12514a16131SFabio EstevamDATA 4 0x021b001c 0x05208030 126*eb5c1807SFabio Estevam/* DDR device ZQ calibration */ 12714a16131SFabio EstevamDATA 4 0x021b001c 0x04008040 128*eb5c1807SFabio Estevam 129*eb5c1807SFabio Estevam/* Final DDR setup, before operation start */ 13014a16131SFabio EstevamDATA 4 0x021b0020 0x00000800 13114a16131SFabio EstevamDATA 4 0x021b0818 0x00011117 13214a16131SFabio EstevamDATA 4 0x021b001c 0x00000000 133