1*cf94a342SYe Li/* 2*cf94a342SYe Li * Copyright (C) 2014 Freescale Semiconductor, Inc. 3*cf94a342SYe Li * 4*cf94a342SYe Li * SPDX-License-Identifier: GPL-2.0+ 5*cf94a342SYe Li */ 6*cf94a342SYe Li 7*cf94a342SYe Li#define __ASSEMBLY__ 8*cf94a342SYe Li#include <config.h> 9*cf94a342SYe Li 10*cf94a342SYe Li/* image version */ 11*cf94a342SYe Li 12*cf94a342SYe LiIMAGE_VERSION 2 13*cf94a342SYe Li 14*cf94a342SYe Li/* 15*cf94a342SYe Li * Boot Device : one of 16*cf94a342SYe Li * spi/sd/nand/onenand, qspi/nor 17*cf94a342SYe Li */ 18*cf94a342SYe Li 19*cf94a342SYe LiBOOT_FROM sd 20*cf94a342SYe Li 21*cf94a342SYe Li/* 22*cf94a342SYe Li * Device Configuration Data (DCD) 23*cf94a342SYe Li * 24*cf94a342SYe Li * Each entry must have the format: 25*cf94a342SYe Li * Addr-type Address Value 26*cf94a342SYe Li * 27*cf94a342SYe Li * where: 28*cf94a342SYe Li * Addr-type register length (1,2 or 4 bytes) 29*cf94a342SYe Li * Address absolute address of the register 30*cf94a342SYe Li * value value to be stored in the register 31*cf94a342SYe Li */ 32*cf94a342SYe Li 33*cf94a342SYe Li/* Enable all clocks */ 34*cf94a342SYe LiDATA 4 0x020c4068 0xffffffff 35*cf94a342SYe LiDATA 4 0x020c406c 0xffffffff 36*cf94a342SYe LiDATA 4 0x020c4070 0xffffffff 37*cf94a342SYe LiDATA 4 0x020c4074 0xffffffff 38*cf94a342SYe LiDATA 4 0x020c4078 0xffffffff 39*cf94a342SYe LiDATA 4 0x020c407c 0xffffffff 40*cf94a342SYe LiDATA 4 0x020c4080 0xffffffff 41*cf94a342SYe LiDATA 4 0x020c4084 0xffffffff 42*cf94a342SYe Li 43*cf94a342SYe Li/* IOMUX - DDR IO Type */ 44*cf94a342SYe LiDATA 4 0x020e0618 0x000c0000 45*cf94a342SYe LiDATA 4 0x020e05fc 0x00000000 46*cf94a342SYe Li 47*cf94a342SYe Li/* Clock */ 48*cf94a342SYe LiDATA 4 0x020e032c 0x00000030 49*cf94a342SYe Li 50*cf94a342SYe Li/* Address */ 51*cf94a342SYe LiDATA 4 0x020e0300 0x00000030 52*cf94a342SYe LiDATA 4 0x020e02fc 0x00000030 53*cf94a342SYe LiDATA 4 0x020e05f4 0x00000030 54*cf94a342SYe Li 55*cf94a342SYe Li/* Control */ 56*cf94a342SYe LiDATA 4 0x020e0340 0x00000030 57*cf94a342SYe Li 58*cf94a342SYe LiDATA 4 0x020e0320 0x00000000 59*cf94a342SYe LiDATA 4 0x020e0310 0x00000030 60*cf94a342SYe LiDATA 4 0x020e0314 0x00000030 61*cf94a342SYe LiDATA 4 0x020e0614 0x00000030 62*cf94a342SYe Li 63*cf94a342SYe Li/* Data Strobe */ 64*cf94a342SYe LiDATA 4 0x020e05f8 0x00020000 65*cf94a342SYe LiDATA 4 0x020e0330 0x00000030 66*cf94a342SYe LiDATA 4 0x020e0334 0x00000030 67*cf94a342SYe LiDATA 4 0x020e0338 0x00000030 68*cf94a342SYe LiDATA 4 0x020e033c 0x00000030 69*cf94a342SYe Li 70*cf94a342SYe Li/* Data */ 71*cf94a342SYe LiDATA 4 0x020e0608 0x00020000 72*cf94a342SYe LiDATA 4 0x020e060c 0x00000030 73*cf94a342SYe LiDATA 4 0x020e0610 0x00000030 74*cf94a342SYe LiDATA 4 0x020e061c 0x00000030 75*cf94a342SYe LiDATA 4 0x020e0620 0x00000030 76*cf94a342SYe LiDATA 4 0x020e02ec 0x00000030 77*cf94a342SYe LiDATA 4 0x020e02f0 0x00000030 78*cf94a342SYe LiDATA 4 0x020e02f4 0x00000030 79*cf94a342SYe LiDATA 4 0x020e02f8 0x00000030 80*cf94a342SYe Li 81*cf94a342SYe Li/* Calibrations - ZQ */ 82*cf94a342SYe LiDATA 4 0x021b0800 0xa1390003 83*cf94a342SYe Li 84*cf94a342SYe Li/* Write leveling */ 85*cf94a342SYe LiDATA 4 0x021b080c 0x002C003D 86*cf94a342SYe LiDATA 4 0x021b0810 0x00110046 87*cf94a342SYe Li 88*cf94a342SYe Li/* DQS Read Gate */ 89*cf94a342SYe LiDATA 4 0x021b083c 0x4160016C 90*cf94a342SYe LiDATA 4 0x021b0840 0x013C016C 91*cf94a342SYe Li 92*cf94a342SYe Li/* Read/Write Delay */ 93*cf94a342SYe LiDATA 4 0x021b0848 0x46424446 94*cf94a342SYe LiDATA 4 0x021b0850 0x3A3C3C3A 95*cf94a342SYe Li 96*cf94a342SYe LiDATA 4 0x021b08c0 0x2492244A 97*cf94a342SYe Li 98*cf94a342SYe Li/* read data bit delay */ 99*cf94a342SYe LiDATA 4 0x021b081c 0x33333333 100*cf94a342SYe LiDATA 4 0x021b0820 0x33333333 101*cf94a342SYe LiDATA 4 0x021b0824 0x33333333 102*cf94a342SYe LiDATA 4 0x021b0828 0x33333333 103*cf94a342SYe Li 104*cf94a342SYe Li/* Complete calibration by forced measurement */ 105*cf94a342SYe LiDATA 4 0x021b08b8 0x00000800 106*cf94a342SYe Li 107*cf94a342SYe Li/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */ 108*cf94a342SYe LiDATA 4 0x021b0004 0x0002002d 109*cf94a342SYe LiDATA 4 0x021b0008 0x00333030 110*cf94a342SYe LiDATA 4 0x021b000c 0x676b52f3 111*cf94a342SYe LiDATA 4 0x021b0010 0xb66d8b63 112*cf94a342SYe LiDATA 4 0x021b0014 0x01ff00db 113*cf94a342SYe LiDATA 4 0x021b0018 0x00011740 114*cf94a342SYe LiDATA 4 0x021b001c 0x00008000 115*cf94a342SYe LiDATA 4 0x021b002c 0x000026d2 116*cf94a342SYe LiDATA 4 0x021b0030 0x006b1023 117*cf94a342SYe LiDATA 4 0x021b0040 0x0000007f 118*cf94a342SYe LiDATA 4 0x021b0000 0x85190000 119*cf94a342SYe Li 120*cf94a342SYe Li/* Initialize MT41K256M16HA-125 - MR2 */ 121*cf94a342SYe LiDATA 4 0x021b001c 0x04008032 122*cf94a342SYe Li/* MR3 */ 123*cf94a342SYe LiDATA 4 0x021b001c 0x00008033 124*cf94a342SYe Li/* MR1 */ 125*cf94a342SYe LiDATA 4 0x021b001c 0x00068031 126*cf94a342SYe Li/* MR0 */ 127*cf94a342SYe LiDATA 4 0x021b001c 0x05208030 128*cf94a342SYe Li/* DDR device ZQ calibration */ 129*cf94a342SYe LiDATA 4 0x021b001c 0x04008040 130*cf94a342SYe Li 131*cf94a342SYe Li/* Final DDR setup, before operation start */ 132*cf94a342SYe LiDATA 4 0x021b0020 0x00000800 133*cf94a342SYe LiDATA 4 0x021b0818 0x00022227 134*cf94a342SYe LiDATA 4 0x021b0004 0x0002556d 135*cf94a342SYe LiDATA 4 0x021b0404 0x00011006 136*cf94a342SYe LiDATA 4 0x021b001c 0x00000000 137