1 /* 2 * (C) Copyright 2009 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <asm/io.h> 25 #include <asm/arch/imx-regs.h> 26 #include <asm/arch/mx51_pins.h> 27 #include <asm/arch/iomux.h> 28 #include <asm/errno.h> 29 #include <i2c.h> 30 #include <mmc.h> 31 #include <fsl_esdhc.h> 32 #include "mx51evk.h" 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 static u32 system_rev; 37 struct io_board_ctrl *mx51_io_board; 38 39 #ifdef CONFIG_FSL_ESDHC 40 struct fsl_esdhc_cfg esdhc_cfg[2] = { 41 {MMC_SDHC1_BASE_ADDR, 1, 1}, 42 {MMC_SDHC2_BASE_ADDR, 1, 1}, 43 }; 44 #endif 45 46 u32 get_board_rev(void) 47 { 48 return system_rev; 49 } 50 51 static inline void set_board_rev(int rev) 52 { 53 system_rev |= (rev & 0xF) << 8; 54 } 55 56 inline int is_soc_rev(int rev) 57 { 58 return (system_rev & 0xFF) - rev; 59 } 60 61 int dram_init(void) 62 { 63 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 64 gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, 65 PHYS_SDRAM_1_SIZE); 66 return 0; 67 } 68 69 static void setup_iomux_uart(void) 70 { 71 unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | 72 PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH; 73 74 mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0); 75 mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST); 76 mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0); 77 mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST); 78 mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0); 79 mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad); 80 mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0); 81 mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad); 82 } 83 84 static void setup_expio(void) 85 { 86 u32 reg; 87 struct weim *pweim = (struct weim *)WEIM_BASE_ADDR; 88 struct clkctl *pclkctl = (struct clkctl *)CCM_BASE_ADDR; 89 90 /* CS5 setup */ 91 mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT0); 92 writel(0x00410089, &pweim[5].csgcr1); 93 writel(0x00000002, &pweim[5].csgcr2); 94 95 /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */ 96 writel(0x32260000, &pweim[5].csrcr1); 97 98 /* APR = 0 */ 99 writel(0x00000000, &pweim[5].csrcr2); 100 101 /* 102 * WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0, 103 * WCSA=0, WCSN=0 104 */ 105 writel(0x72080F00, &pweim[5].cswcr1); 106 107 mx51_io_board = (struct io_board_ctrl *)(CS5_BASE_ADDR + 108 IO_BOARD_OFFSET); 109 if ((readw(&mx51_io_board->id1) == 0xAAAA) && 110 (readw(&mx51_io_board->id2) == 0x5555)) { 111 if (is_soc_rev(CHIP_REV_2_0) < 0) { 112 reg = readl(&pclkctl->cbcdr); 113 reg = (reg & (~0x70000)) | 0x30000; 114 writel(reg, &pclkctl->cbcdr); 115 /* make sure divider effective */ 116 while (readl(&pclkctl->cdhipr) != 0) 117 ; 118 writel(0x0, &pclkctl->ccdr); 119 } 120 } else { 121 /* CS1 */ 122 writel(0x00410089, &pweim[1].csgcr1); 123 writel(0x00000002, &pweim[1].csgcr2); 124 /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */ 125 writel(0x32260000, &pweim[1].csrcr1); 126 /* APR=0 */ 127 writel(0x00000000, &pweim[1].csrcr2); 128 /* 129 * WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, 130 * WEN=0, WCSA=0, WCSN=0 131 */ 132 writel(0x72080F00, &pweim[1].cswcr1); 133 mx51_io_board = (struct io_board_ctrl *)(CS1_BASE_ADDR + 134 IO_BOARD_OFFSET); 135 } 136 137 /* Reset interrupt status reg */ 138 writew(0x1F, &(mx51_io_board->int_rest)); 139 writew(0x00, &(mx51_io_board->int_rest)); 140 writew(0xFFFF, &(mx51_io_board->int_mask)); 141 142 /* Reset the XUART and Ethernet controllers */ 143 reg = readw(&(mx51_io_board->sw_reset)); 144 reg |= 0x9; 145 writew(reg, &(mx51_io_board->sw_reset)); 146 reg &= ~0x9; 147 writew(reg, &(mx51_io_board->sw_reset)); 148 } 149 150 static void setup_iomux_fec(void) 151 { 152 /*FEC_MDIO*/ 153 mxc_request_iomux(MX51_PIN_EIM_EB2 , IOMUX_CONFIG_ALT3); 154 mxc_iomux_set_pad(MX51_PIN_EIM_EB2 , 0x1FD); 155 156 /*FEC_MDC*/ 157 mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2); 158 mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004); 159 160 /* FEC RDATA[3] */ 161 mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3); 162 mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180); 163 164 /* FEC RDATA[2] */ 165 mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3); 166 mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180); 167 168 /* FEC RDATA[1] */ 169 mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3); 170 mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180); 171 172 /* FEC RDATA[0] */ 173 mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2); 174 mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180); 175 176 /* FEC TDATA[3] */ 177 mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2); 178 mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004); 179 180 /* FEC TDATA[2] */ 181 mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2); 182 mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004); 183 184 /* FEC TDATA[1] */ 185 mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2); 186 mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004); 187 188 /* FEC TDATA[0] */ 189 mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2); 190 mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004); 191 192 /* FEC TX_EN */ 193 mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1); 194 mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004); 195 196 /* FEC TX_ER */ 197 mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2); 198 mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004); 199 200 /* FEC TX_CLK */ 201 mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1); 202 mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180); 203 204 /* FEC TX_COL */ 205 mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1); 206 mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180); 207 208 /* FEC RX_CLK */ 209 mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1); 210 mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180); 211 212 /* FEC RX_CRS */ 213 mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3); 214 mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180); 215 216 /* FEC RX_ER */ 217 mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3); 218 mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180); 219 220 /* FEC RX_DV */ 221 mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2); 222 mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180); 223 } 224 225 #ifdef CONFIG_FSL_ESDHC 226 int board_mmc_getcd(u8 *cd, struct mmc *mmc) 227 { 228 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 229 230 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) 231 *cd = readl(GPIO1_BASE_ADDR) & 0x01; 232 else 233 *cd = readl(GPIO1_BASE_ADDR) & 0x40; 234 235 return 0; 236 } 237 238 int board_mmc_init(bd_t *bis) 239 { 240 u32 index; 241 s32 status = 0; 242 243 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; 244 index++) { 245 switch (index) { 246 case 0: 247 mxc_request_iomux(MX51_PIN_SD1_CMD, 248 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 249 mxc_request_iomux(MX51_PIN_SD1_CLK, 250 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 251 mxc_request_iomux(MX51_PIN_SD1_DATA0, 252 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 253 mxc_request_iomux(MX51_PIN_SD1_DATA1, 254 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 255 mxc_request_iomux(MX51_PIN_SD1_DATA2, 256 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 257 mxc_request_iomux(MX51_PIN_SD1_DATA3, 258 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 259 mxc_iomux_set_pad(MX51_PIN_SD1_CMD, 260 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | 261 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | 262 PAD_CTL_PUE_PULL | 263 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); 264 mxc_iomux_set_pad(MX51_PIN_SD1_CLK, 265 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | 266 PAD_CTL_HYS_NONE | PAD_CTL_47K_PU | 267 PAD_CTL_PUE_PULL | 268 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); 269 mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, 270 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | 271 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | 272 PAD_CTL_PUE_PULL | 273 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); 274 mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, 275 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | 276 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | 277 PAD_CTL_PUE_PULL | 278 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); 279 mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, 280 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | 281 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | 282 PAD_CTL_PUE_PULL | 283 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); 284 mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, 285 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | 286 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD | 287 PAD_CTL_PUE_PULL | 288 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); 289 mxc_request_iomux(MX51_PIN_GPIO1_0, 290 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 291 mxc_iomux_set_pad(MX51_PIN_GPIO1_0, 292 PAD_CTL_HYS_ENABLE); 293 mxc_request_iomux(MX51_PIN_GPIO1_1, 294 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 295 mxc_iomux_set_pad(MX51_PIN_GPIO1_1, 296 PAD_CTL_HYS_ENABLE); 297 break; 298 case 1: 299 mxc_request_iomux(MX51_PIN_SD2_CMD, 300 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 301 mxc_request_iomux(MX51_PIN_SD2_CLK, 302 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 303 mxc_request_iomux(MX51_PIN_SD2_DATA0, 304 IOMUX_CONFIG_ALT0); 305 mxc_request_iomux(MX51_PIN_SD2_DATA1, 306 IOMUX_CONFIG_ALT0); 307 mxc_request_iomux(MX51_PIN_SD2_DATA2, 308 IOMUX_CONFIG_ALT0); 309 mxc_request_iomux(MX51_PIN_SD2_DATA3, 310 IOMUX_CONFIG_ALT0); 311 mxc_iomux_set_pad(MX51_PIN_SD2_CMD, 312 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | 313 PAD_CTL_SRE_FAST); 314 mxc_iomux_set_pad(MX51_PIN_SD2_CLK, 315 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | 316 PAD_CTL_SRE_FAST); 317 mxc_iomux_set_pad(MX51_PIN_SD2_DATA0, 318 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | 319 PAD_CTL_SRE_FAST); 320 mxc_iomux_set_pad(MX51_PIN_SD2_DATA1, 321 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | 322 PAD_CTL_SRE_FAST); 323 mxc_iomux_set_pad(MX51_PIN_SD2_DATA2, 324 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | 325 PAD_CTL_SRE_FAST); 326 mxc_iomux_set_pad(MX51_PIN_SD2_DATA3, 327 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | 328 PAD_CTL_SRE_FAST); 329 mxc_request_iomux(MX51_PIN_SD2_CMD, 330 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 331 mxc_request_iomux(MX51_PIN_GPIO1_6, 332 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 333 mxc_iomux_set_pad(MX51_PIN_GPIO1_6, 334 PAD_CTL_HYS_ENABLE); 335 mxc_request_iomux(MX51_PIN_GPIO1_5, 336 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); 337 mxc_iomux_set_pad(MX51_PIN_GPIO1_5, 338 PAD_CTL_HYS_ENABLE); 339 break; 340 default: 341 printf("Warning: you configured more ESDHC controller" 342 "(%d) as supported by the board(2)\n", 343 CONFIG_SYS_FSL_ESDHC_NUM); 344 return status; 345 } 346 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); 347 } 348 return status; 349 } 350 #endif 351 352 int board_init(void) 353 { 354 system_rev = get_cpu_rev(); 355 356 gd->bd->bi_arch_number = MACH_TYPE_MX51_BABBAGE; 357 /* address of boot parameters */ 358 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 359 360 setup_iomux_uart(); 361 setup_expio(); 362 setup_iomux_fec(); 363 return 0; 364 } 365 366 int checkboard(void) 367 { 368 puts("Board: MX51EVK "); 369 370 switch (system_rev & 0xff) { 371 case CHIP_REV_3_0: 372 puts("3.0 ["); 373 break; 374 case CHIP_REV_2_5: 375 puts("2.5 ["); 376 break; 377 case CHIP_REV_2_0: 378 puts("2.0 ["); 379 break; 380 case CHIP_REV_1_1: 381 puts("1.1 ["); 382 break; 383 case CHIP_REV_1_0: 384 default: 385 puts("1.0 ["); 386 break; 387 } 388 389 switch (__raw_readl(SRC_BASE_ADDR + 0x8)) { 390 case 0x0001: 391 puts("POR"); 392 break; 393 case 0x0009: 394 puts("RST"); 395 break; 396 case 0x0010: 397 case 0x0011: 398 puts("WDOG"); 399 break; 400 default: 401 puts("unknown"); 402 } 403 puts("]\n"); 404 return 0; 405 } 406 407