xref: /rk3399_rockchip-uboot/board/freescale/mx35pdk/mx35pdk.h (revision 326ea986ac150acdc7656d57fca647db80b50158)
1eae4988bSStefano Babic /*
2eae4988bSStefano Babic  *
3eae4988bSStefano Babic  * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
4eae4988bSStefano Babic  *
5eae4988bSStefano Babic  * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
6eae4988bSStefano Babic  *
7*1a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
8eae4988bSStefano Babic  */
9eae4988bSStefano Babic 
10eae4988bSStefano Babic #ifndef __BOARD_MX35_3STACK_H
11eae4988bSStefano Babic #define __BOARD_MX35_3STACK_H
12eae4988bSStefano Babic 
13eae4988bSStefano Babic #define DBG_BASE_ADDR		WEIM_CTRL_CS5
14eae4988bSStefano Babic #define DBG_CSCR_U_CONFIG	0x0000D843
15eae4988bSStefano Babic #define DBG_CSCR_L_CONFIG	0x22252521
16eae4988bSStefano Babic #define DBG_CSCR_A_CONFIG	0x22220A00
17eae4988bSStefano Babic 
18eae4988bSStefano Babic #define CCM_CCMR_CONFIG		0x003F4208
19eae4988bSStefano Babic #define CCM_PDR0_CONFIG		0x00801000
20eae4988bSStefano Babic 
21eae4988bSStefano Babic /* MEMORY SETTING */
22eae4988bSStefano Babic #define ESDCTL_0x92220000	0x92220000
23eae4988bSStefano Babic #define ESDCTL_0xA2220000	0xA2220000
24eae4988bSStefano Babic #define ESDCTL_0xB2220000	0xB2220000
25eae4988bSStefano Babic #define ESDCTL_0x82228080	0x82228080
26eae4988bSStefano Babic 
27eae4988bSStefano Babic #define ESDCTL_PRECHARGE	0x00000400
28eae4988bSStefano Babic 
29eae4988bSStefano Babic #define ESDCTL_MDDR_CONFIG	0x007FFC3F
30eae4988bSStefano Babic #define ESDCTL_MDDR_MR		0x00000033
31eae4988bSStefano Babic #define ESDCTL_MDDR_EMR		0x02000000
32eae4988bSStefano Babic 
33eae4988bSStefano Babic #define ESDCTL_DDR2_CONFIG	0x007FFC3F
34eae4988bSStefano Babic #define ESDCTL_DDR2_EMR2	0x04000000
35eae4988bSStefano Babic #define ESDCTL_DDR2_EMR3	0x06000000
36eae4988bSStefano Babic #define ESDCTL_DDR2_EN_DLL	0x02000400
37eae4988bSStefano Babic #define ESDCTL_DDR2_RESET_DLL	0x00000333
38eae4988bSStefano Babic #define ESDCTL_DDR2_MR		0x00000233
39eae4988bSStefano Babic #define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
40eae4988bSStefano Babic 
41eae4988bSStefano Babic #define ESDCTL_DELAY_LINE5	0x00F49F00
42eae4988bSStefano Babic #endif				/* __BOARD_MX35_3STACK_H */
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