1*d08e5ca3SMagnus Lilja/* 2*d08e5ca3SMagnus Lilja * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com> 3*d08e5ca3SMagnus Lilja * 4*d08e5ca3SMagnus Lilja * See file CREDITS for list of people who contributed to this 5*d08e5ca3SMagnus Lilja * project. 6*d08e5ca3SMagnus Lilja * 7*d08e5ca3SMagnus Lilja * This program is free software; you can redistribute it and/or 8*d08e5ca3SMagnus Lilja * modify it under the terms of the GNU General Public License as 9*d08e5ca3SMagnus Lilja * published by the Free Software Foundation; either version 2 of 10*d08e5ca3SMagnus Lilja * the License, or (at your option) any later version. 11*d08e5ca3SMagnus Lilja * 12*d08e5ca3SMagnus Lilja * This program is distributed in the hope that it will be useful, 13*d08e5ca3SMagnus Lilja * but WITHOUT ANY WARRANTY; without even the implied warranty of 14*d08e5ca3SMagnus Lilja * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15*d08e5ca3SMagnus Lilja * GNU General Public License for more details. 16*d08e5ca3SMagnus Lilja * 17*d08e5ca3SMagnus Lilja * You should have received a copy of the GNU General Public License 18*d08e5ca3SMagnus Lilja * along with this program; if not, write to the Free Software 19*d08e5ca3SMagnus Lilja * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20*d08e5ca3SMagnus Lilja * MA 02111-1307 USA 21*d08e5ca3SMagnus Lilja */ 22*d08e5ca3SMagnus Lilja 23*d08e5ca3SMagnus Lilja#include <config.h> 24*d08e5ca3SMagnus Lilja#include <asm/arch/mx31-regs.h> 25*d08e5ca3SMagnus Lilja#include <asm/macro.h> 26*d08e5ca3SMagnus Lilja 27*d08e5ca3SMagnus Lilja.globl lowlevel_init 28*d08e5ca3SMagnus Liljalowlevel_init: 29*d08e5ca3SMagnus Lilja /* Also setup the Peripheral Port Remap register inside the core */ 30*d08e5ca3SMagnus Lilja ldr r0, =ARM_PPMRR /* start from AIPS 2GB region */ 31*d08e5ca3SMagnus Lilja mcr p15, 0, r0, c15, c2, 4 32*d08e5ca3SMagnus Lilja 33*d08e5ca3SMagnus Lilja write32 IPU_CONF, IPU_CONF_DI_EN 34*d08e5ca3SMagnus Lilja write32 CCM_CCMR, CCM_CCMR_SETUP 35*d08e5ca3SMagnus Lilja 36*d08e5ca3SMagnus Lilja wait_timer 0x40000 37*d08e5ca3SMagnus Lilja 38*d08e5ca3SMagnus Lilja write32 CCM_CCMR, CCM_CCMR_SETUP | CCMR_MPE 39*d08e5ca3SMagnus Lilja write32 CCM_CCMR, (CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS 40*d08e5ca3SMagnus Lilja 41*d08e5ca3SMagnus Lilja /* Set up clock to 532MHz */ 42*d08e5ca3SMagnus Lilja write32 CCM_PDR0, CCM_PDR0_SETUP_532MHZ 43*d08e5ca3SMagnus Lilja write32 CCM_MPCTL, CCM_MPCTL_SETUP_532MHZ 44*d08e5ca3SMagnus Lilja 45*d08e5ca3SMagnus Lilja write32 CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1) 46*d08e5ca3SMagnus Lilja 47*d08e5ca3SMagnus Lilja /* Set up MX31 DDR pins */ 48*d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B, 0 49*d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0, 0 50*d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_BCLK_RW_RAS, 0 51*d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_CS2_CS3_CS4, 0x1000 52*d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1, 0 53*d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2, 0 54*d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_SD29_SD30_SD31, 0 55*d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_SD26_SD27_SD28, 0 56*d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_SD23_SD24_SD25, 0 57*d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_SD20_SD21_SD22, 0 58*d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_SD17_SD18_SD19, 0 59*d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_SD14_SD15_SD16, 0 60*d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_SD11_SD12_SD13, 0 61*d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_SD8_SD9_SD10, 0 62*d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_SD5_SD6_SD7, 0 63*d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_SD2_SD3_SD4, 0 64*d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1, 0 65*d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_A24_A25_SDBA1, 0 66*d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_A21_A22_A23, 0 67*d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_A18_A19_A20, 0 68*d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_A15_A16_A17, 0 69*d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_A12_A13_A14, 0 70*d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_A10_MA10_A11, 0 71*d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_A7_A8_A9, 0 72*d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_A4_A5_A6, 0 73*d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_A1_A2_A3, 0 74*d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0, 0 75*d08e5ca3SMagnus Lilja 76*d08e5ca3SMagnus Lilja /* Set up MX31 DDR Memory Controller */ 77*d08e5ca3SMagnus Lilja write32 WEIM_ESDMISC, ESDMISC_MDDR_SETUP 78*d08e5ca3SMagnus Lilja write32 WEIM_ESDCFG0, ESDCFG0_MDDR_SETUP 79*d08e5ca3SMagnus Lilja 80*d08e5ca3SMagnus Lilja /* Perform DDR init sequence */ 81*d08e5ca3SMagnus Lilja write32 WEIM_ESDCTL0, ESDCTL_PRECHARGE 82*d08e5ca3SMagnus Lilja write32 CSD0_BASE | 0x0f00, 0x12344321 83*d08e5ca3SMagnus Lilja write32 WEIM_ESDCTL0, ESDCTL_AUTOREFRESH 84*d08e5ca3SMagnus Lilja write32 CSD0_BASE, 0x12344321 85*d08e5ca3SMagnus Lilja write32 CSD0_BASE, 0x12344321 86*d08e5ca3SMagnus Lilja write32 WEIM_ESDCTL0, ESDCTL_LOADMODEREG 87*d08e5ca3SMagnus Lilja write8 CSD0_BASE | 0x00000033, 0xda 88*d08e5ca3SMagnus Lilja write8 CSD0_BASE | 0x01000000, 0xff 89*d08e5ca3SMagnus Lilja write32 WEIM_ESDCTL0, ESDCTL_RW 90*d08e5ca3SMagnus Lilja write32 CSD0_BASE, 0xDEADBEEF 91*d08e5ca3SMagnus Lilja write32 WEIM_ESDMISC, ESDMISC_MDDR_RESET_DL 92*d08e5ca3SMagnus Lilja 93*d08e5ca3SMagnus Lilja mov pc, lr 94