1 /* 2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <netdev.h> 25 #include <asm/io.h> 26 #include <asm/arch/clock.h> 27 #include <asm/arch/imx-regs.h> 28 #include <asm/arch/sys_proto.h> 29 30 DECLARE_GLOBAL_DATA_PTR; 31 32 int dram_init(void) 33 { 34 /* dram_init must store complete ramsize in gd->ram_size */ 35 gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, 36 PHYS_SDRAM_1_SIZE); 37 return 0; 38 } 39 40 int board_early_init_f(void) 41 { 42 int i; 43 44 /* CS0: Nor Flash */ 45 /* 46 * CS0L and CS0A values are from the RedBoot sources by Freescale 47 * and are also equal to those used by Sascha Hauer for the Phytec 48 * i.MX31 board. CS0U is just a slightly optimized hardware default: 49 * the only non-zero field "Wait State Control" is set to half the 50 * default value. 51 */ 52 static const struct mxc_weimcs cs0 = { 53 /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ 54 CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0), 55 /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ 56 CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1), 57 /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ 58 CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0) 59 }; 60 61 mxc_setup_weimcs(0, &cs0); 62 63 /* setup pins for UART1 */ 64 mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); 65 mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX); 66 mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); 67 mx31_gpio_mux(MUX_CTS1__UART1_CTS_B); 68 69 /* SPI2 */ 70 mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B); 71 mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK); 72 mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B); 73 mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI); 74 mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO); 75 mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B); 76 mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B); 77 78 /* start SPI2 clock */ 79 __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4); 80 81 /* PBC setup */ 82 /* Enable UART transceivers also reset the Ethernet/external UART */ 83 readw(CS4_BASE + 4); 84 85 writew(0x8023, CS4_BASE + 4); 86 87 /* RedBoot also has an empty loop with 100000 iterations here - 88 * clock doesn't run yet */ 89 for (i = 0; i < 100000; i++) 90 ; 91 92 /* Clear the reset, toggle the LEDs */ 93 writew(0xDF, CS4_BASE + 6); 94 95 /* clock still doesn't run */ 96 for (i = 0; i < 100000; i++) 97 ; 98 99 /* See 1.5.4 in IMX31ADSE_PERI_BUS_CNTRL_CPLD_RM.pdf */ 100 readb(CS4_BASE + 8); 101 readb(CS4_BASE + 7); 102 readb(CS4_BASE + 8); 103 readb(CS4_BASE + 7); 104 105 return 0; 106 } 107 108 int board_init(void) 109 { 110 gd->bd->bi_boot_params = 0x80000100; /* adress of boot parameters */ 111 112 return 0; 113 } 114 115 int checkboard(void) 116 { 117 printf("Board: MX31ADS\n"); 118 return 0; 119 } 120 121 #ifdef CONFIG_CMD_NET 122 int board_eth_init(bd_t *bis) 123 { 124 int rc = 0; 125 #ifdef CONFIG_CS8900 126 rc = cs8900_initialize(0, CONFIG_CS8900_BASE); 127 #endif 128 return rc; 129 } 130 #endif 131