1 /* 2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <asm/io.h> 25 #include <asm/arch/mx31.h> 26 #include <asm/arch/mx31-regs.h> 27 28 DECLARE_GLOBAL_DATA_PTR; 29 30 int dram_init (void) 31 { 32 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 33 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; 34 35 return 0; 36 } 37 38 int board_init (void) 39 { 40 int i; 41 42 /* CS0: Nor Flash */ 43 /* 44 * CS0L and CS0A values are from the RedBoot sources by Freescale 45 * and are also equal to those used by Sascha Hauer for the Phytec 46 * i.MX31 board. CS0U is just a slightly optimized hardware default: 47 * the only non-zero field "Wait State Control" is set to half the 48 * default value. 49 */ 50 __REG(CSCR_U(0)) = 0x00000f00; 51 __REG(CSCR_L(0)) = 0x10000D03; 52 __REG(CSCR_A(0)) = 0x00720900; 53 54 /* setup pins for UART1 */ 55 mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); 56 mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX); 57 mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); 58 mx31_gpio_mux(MUX_CTS1__UART1_CTS_B); 59 60 /* SPI2 */ 61 mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B); 62 mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK); 63 mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B); 64 mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI); 65 mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO); 66 mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B); 67 mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B); 68 69 /* start SPI2 clock */ 70 __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4); 71 72 /* PBC setup */ 73 /* Enable UART transceivers also reset the Ethernet/external UART */ 74 readw(CS4_BASE + 4); 75 76 writew(0x8023, CS4_BASE + 4); 77 78 /* RedBoot also has an empty loop with 100000 iterations here - 79 * clock doesn't run yet */ 80 for (i = 0; i < 100000; i++) 81 ; 82 83 /* Clear the reset, toggle the LEDs */ 84 writew(0xDF, CS4_BASE + 6); 85 86 /* clock still doesn't run */ 87 for (i = 0; i < 100000; i++) 88 ; 89 90 /* See 1.5.4 in IMX31ADSE_PERI_BUS_CNTRL_CPLD_RM.pdf */ 91 readb(CS4_BASE + 8); 92 readb(CS4_BASE + 7); 93 readb(CS4_BASE + 8); 94 readb(CS4_BASE + 7); 95 96 gd->bd->bi_arch_number = MACH_TYPE_MX31ADS; /* board id for linux */ 97 gd->bd->bi_boot_params = 0x80000100; /* adress of boot parameters */ 98 99 return 0; 100 } 101 102 int checkboard (void) 103 { 104 printf("Board: MX31ADS\n"); 105 return 0; 106 } 107