1 /* 2 * Copyright 2007,2009 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/immap_86xx.h> 28 #include <asm/fsl_pci.h> 29 #include <asm/fsl_ddr_sdram.h> 30 #include <i2c.h> 31 #include <asm/io.h> 32 #include <libfdt.h> 33 #include <fdt_support.h> 34 #include <spd_sdram.h> 35 #include <netdev.h> 36 37 #include "../common/pixis.h" 38 39 void sdram_init(void); 40 phys_size_t fixed_sdram(void); 41 void mpc8610hpcd_diu_init(void); 42 43 44 /* called before any console output */ 45 int board_early_init_f(void) 46 { 47 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 48 volatile ccsr_gur_t *gur = &immap->im_gur; 49 50 gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */ 51 52 return 0; 53 } 54 55 int misc_init_r(void) 56 { 57 u8 tmp_val, version; 58 u8 *pixis_base = (u8 *)PIXIS_BASE; 59 60 /*Do not use 8259PIC*/ 61 tmp_val = in_8(pixis_base + PIXIS_BRDCFG0); 62 out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80); 63 64 /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/ 65 version = in_8(pixis_base + PIXIS_PVER); 66 if(version >= 0x07) { 67 tmp_val = in_8(pixis_base + PIXIS_BRDCFG0); 68 out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf); 69 } 70 71 /* Using this for DIU init before the driver in linux takes over 72 * Enable the TFP410 Encoder (I2C address 0x38) 73 */ 74 75 tmp_val = 0xBF; 76 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); 77 /* Verify if enabled */ 78 tmp_val = 0; 79 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); 80 debug("DVI Encoder Read: 0x%02lx\n",tmp_val); 81 82 tmp_val = 0x10; 83 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); 84 /* Verify if enabled */ 85 tmp_val = 0; 86 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); 87 debug("DVI Encoder Read: 0x%02lx\n",tmp_val); 88 89 #ifdef CONFIG_FSL_DIU_FB 90 mpc8610hpcd_diu_init(); 91 #endif 92 93 return 0; 94 } 95 96 int checkboard(void) 97 { 98 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 99 volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; 100 u8 *pixis_base = (u8 *)PIXIS_BASE; 101 102 printf ("Board: MPC8610HPCD, System ID: 0x%02x, " 103 "System Version: 0x%02x, FPGA Version: 0x%02x\n", 104 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 105 in_8(pixis_base + PIXIS_PVER)); 106 107 mcm->abcr |= 0x00010000; /* 0 */ 108 mcm->hpmr3 = 0x80000008; /* 4c */ 109 mcm->hpmr0 = 0; 110 mcm->hpmr1 = 0; 111 mcm->hpmr2 = 0; 112 mcm->hpmr4 = 0; 113 mcm->hpmr5 = 0; 114 115 return 0; 116 } 117 118 119 phys_size_t 120 initdram(int board_type) 121 { 122 phys_size_t dram_size = 0; 123 124 #if defined(CONFIG_SPD_EEPROM) 125 dram_size = fsl_ddr_sdram(); 126 #else 127 dram_size = fixed_sdram(); 128 #endif 129 130 setup_ddr_bat(dram_size); 131 132 puts(" DDR: "); 133 return dram_size; 134 } 135 136 137 #if !defined(CONFIG_SPD_EEPROM) 138 /* 139 * Fixed sdram init -- doesn't use serial presence detect. 140 */ 141 142 phys_size_t fixed_sdram(void) 143 { 144 #if !defined(CONFIG_SYS_RAMBOOT) 145 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 146 volatile ccsr_ddr_t *ddr = &immap->im_ddr1; 147 uint d_init; 148 149 ddr->cs0_bnds = 0x0000001f; 150 ddr->cs0_config = 0x80010202; 151 152 ddr->timing_cfg_3 = 0x00000000; 153 ddr->timing_cfg_0 = 0x00260802; 154 ddr->timing_cfg_1 = 0x3935d322; 155 ddr->timing_cfg_2 = 0x14904cc8; 156 ddr->sdram_mode = 0x00480432; 157 ddr->sdram_mode_2 = 0x00000000; 158 ddr->sdram_interval = 0x06180fff; /* 0x06180100; */ 159 ddr->sdram_data_init = 0xDEADBEEF; 160 ddr->sdram_clk_cntl = 0x03800000; 161 ddr->sdram_cfg_2 = 0x04400010; 162 163 #if defined(CONFIG_DDR_ECC) 164 ddr->err_int_en = 0x0000000d; 165 ddr->err_disable = 0x00000000; 166 ddr->err_sbe = 0x00010000; 167 #endif 168 asm("sync;isync"); 169 170 udelay(500); 171 172 ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/ 173 174 175 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 176 d_init = 1; 177 debug("DDR - 1st controller: memory initializing\n"); 178 /* 179 * Poll until memory is initialized. 180 * 512 Meg at 400 might hit this 200 times or so. 181 */ 182 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) 183 udelay(1000); 184 185 debug("DDR: memory initialized\n\n"); 186 asm("sync; isync"); 187 udelay(500); 188 #endif 189 190 return 512 * 1024 * 1024; 191 #endif 192 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 193 } 194 195 #endif 196 197 #if defined(CONFIG_PCI) 198 /* 199 * Initialize PCI Devices, report devices found. 200 */ 201 202 #ifndef CONFIG_PCI_PNP 203 static struct pci_config_table pci_fsl86xxads_config_table[] = { 204 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 205 PCI_IDSEL_NUMBER, PCI_ANY_ID, 206 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, 207 PCI_ENET0_MEMADDR, 208 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} }, 209 {} 210 }; 211 #endif 212 213 214 static struct pci_controller pci1_hose = { 215 #ifndef CONFIG_PCI_PNP 216 config_table:pci_mpc86xxcts_config_table 217 #endif 218 }; 219 #endif /* CONFIG_PCI */ 220 221 #ifdef CONFIG_PCIE1 222 static struct pci_controller pcie1_hose; 223 #endif 224 225 #ifdef CONFIG_PCIE2 226 static struct pci_controller pcie2_hose; 227 #endif 228 229 void pci_init_board(void) 230 { 231 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; 232 volatile ccsr_gur_t *gur = &immap->im_gur; 233 struct fsl_pci_info pci_info[3]; 234 u32 devdisr, pordevsr, io_sel; 235 int first_free_busno = 0; 236 int num = 0; 237 238 int pci_agent, pcie_ep, pcie_configured; 239 240 devdisr = in_be32(&gur->devdisr); 241 pordevsr = in_be32(&gur->pordevsr); 242 io_sel = (pordevsr & MPC8610_PORDEVSR_IO_SEL) 243 >> MPC8610_PORDEVSR_IO_SEL_SHIFT; 244 245 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); 246 247 #ifdef CONFIG_PCIE1 248 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); 249 250 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)){ 251 SET_STD_PCIE_INFO(pci_info[num], 1); 252 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); 253 printf (" PCIE1 connected to ULI as %s (base addr %lx)\n", 254 pcie_ep ? "Endpoint" : "Root Complex", 255 pci_info[num].regs); 256 257 first_free_busno = fsl_pci_init_port(&pci_info[num++], 258 &pcie1_hose, first_free_busno); 259 } else { 260 printf (" PCIE1: disabled\n"); 261 } 262 263 puts("\n"); 264 #else 265 setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE1); /* disable */ 266 #endif 267 268 #ifdef CONFIG_PCIE2 269 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); 270 271 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)){ 272 SET_STD_PCIE_INFO(pci_info[num], 2); 273 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); 274 printf (" PCIE2 connected to Slot as %s (base addr %lx)\n", 275 pcie_ep ? "Endpoint" : "Root Complex", 276 pci_info[num].regs); 277 first_free_busno = fsl_pci_init_port(&pci_info[num++], 278 &pcie2_hose, first_free_busno); 279 } else { 280 printf (" PCIE2: disabled\n"); 281 } 282 283 puts("\n"); 284 #else 285 setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE2); /* disable */ 286 #endif 287 288 #ifdef CONFIG_PCI1 289 if (!(devdisr & MPC86xx_DEVDISR_PCI1)) { 290 SET_STD_PCI_INFO(pci_info[num], 1); 291 pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); 292 printf(" PCI connected to PCI slots as %s" \ 293 " (base address %lx)\n", 294 pci_agent ? "Agent" : "Host", 295 pci_info[num].regs); 296 first_free_busno = fsl_pci_init_port(&pci_info[num++], 297 &pci1_hose, first_free_busno); 298 } else { 299 printf (" PCI: disabled\n"); 300 } 301 302 puts("\n"); 303 #else 304 setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */ 305 #endif 306 } 307 308 #if defined(CONFIG_OF_BOARD_SETUP) 309 void 310 ft_board_setup(void *blob, bd_t *bd) 311 { 312 ft_cpu_setup(blob, bd); 313 314 #ifdef CONFIG_PCI1 315 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); 316 #endif 317 #ifdef CONFIG_PCIE1 318 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); 319 #endif 320 #ifdef CONFIG_PCIE2 321 ft_fsl_pci_setup(blob, "pci2", &pcie2_hose); 322 #endif 323 } 324 #endif 325 326 /* 327 * get_board_sys_clk 328 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ 329 */ 330 331 unsigned long 332 get_board_sys_clk(ulong dummy) 333 { 334 u8 i; 335 ulong val = 0; 336 u8 *pixis_base = (u8 *)PIXIS_BASE; 337 338 i = in_8(pixis_base + PIXIS_SPD); 339 i &= 0x07; 340 341 switch (i) { 342 case 0: 343 val = 33333000; 344 break; 345 case 1: 346 val = 39999600; 347 break; 348 case 2: 349 val = 49999500; 350 break; 351 case 3: 352 val = 66666000; 353 break; 354 case 4: 355 val = 83332500; 356 break; 357 case 5: 358 val = 99999000; 359 break; 360 case 6: 361 val = 133332000; 362 break; 363 case 7: 364 val = 166665000; 365 break; 366 } 367 368 return val; 369 } 370 371 int board_eth_init(bd_t *bis) 372 { 373 return pci_eth_init(bis); 374 } 375 376 void board_reset(void) 377 { 378 u8 *pixis_base = (u8 *)PIXIS_BASE; 379 380 out_8(pixis_base + PIXIS_RST, 0); 381 382 while (1) 383 ; 384 } 385