1 /* 2 * Copyright 2007 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/immap_86xx.h> 28 #include <asm/immap_fsl_pci.h> 29 #include <i2c.h> 30 #include <spd.h> 31 #include <asm/io.h> 32 33 34 #if defined(CONFIG_OF_FLAT_TREE) 35 #include <ft_build.h> 36 extern void ft_cpu_setup(void *blob, bd_t *bd); 37 #endif 38 39 #include "../common/pixis.h" 40 41 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 42 extern void ddr_enable_ecc(unsigned int dram_size); 43 #endif 44 45 #if defined(CONFIG_SPD_EEPROM) 46 #include "spd_sdram.h" 47 #endif 48 49 void sdram_init(void); 50 long int fixed_sdram(void); 51 void mpc8610hpcd_diu_init(void); 52 53 54 /* called before any console output */ 55 int board_early_init_f(void) 56 { 57 volatile immap_t *immap = (immap_t *)CFG_IMMR; 58 volatile ccsr_gur_t *gur = &immap->im_gur; 59 60 gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */ 61 62 return 0; 63 } 64 65 int misc_init_r(void) 66 { 67 u8 tmp_val, version; 68 69 /*Do not use 8259PIC*/ 70 tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0); 71 out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x80); 72 73 /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/ 74 version = in8(PIXIS_BASE + PIXIS_PVER); 75 if(version >= 0x07) { 76 tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0); 77 out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val & 0xbf); 78 } 79 80 /* Using this for DIU init before the driver in linux takes over 81 * Enable the TFP410 Encoder (I2C address 0x38) 82 */ 83 84 tmp_val = 0xBF; 85 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); 86 /* Verify if enabled */ 87 tmp_val = 0; 88 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); 89 debug("DVI Encoder Read: 0x%02lx\n",tmp_val); 90 91 tmp_val = 0x10; 92 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); 93 /* Verify if enabled */ 94 tmp_val = 0; 95 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); 96 debug("DVI Encoder Read: 0x%02lx\n",tmp_val); 97 98 #ifdef CONFIG_FSL_DIU_FB 99 mpc8610hpcd_diu_init(); 100 #endif 101 102 return 0; 103 } 104 105 int checkboard(void) 106 { 107 volatile immap_t *immap = (immap_t *)CFG_IMMR; 108 volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; 109 110 puts("Board: MPC8610HPCD\n"); 111 112 mcm->abcr |= 0x00010000; /* 0 */ 113 mcm->hpmr3 = 0x80000008; /* 4c */ 114 mcm->hpmr0 = 0; 115 mcm->hpmr1 = 0; 116 mcm->hpmr2 = 0; 117 mcm->hpmr4 = 0; 118 mcm->hpmr5 = 0; 119 120 return 0; 121 } 122 123 124 long int 125 initdram(int board_type) 126 { 127 long dram_size = 0; 128 129 #if defined(CONFIG_SPD_EEPROM) 130 dram_size = spd_sdram(); 131 #else 132 dram_size = fixed_sdram(); 133 #endif 134 135 #if defined(CFG_RAMBOOT) 136 puts(" DDR: "); 137 return dram_size; 138 #endif 139 140 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 141 /* 142 * Initialize and enable DDR ECC. 143 */ 144 ddr_enable_ecc(dram_size); 145 #endif 146 147 puts(" DDR: "); 148 return dram_size; 149 } 150 151 152 #if defined(CFG_DRAM_TEST) 153 int 154 testdram(void) 155 { 156 uint *pstart = (uint *) CFG_MEMTEST_START; 157 uint *pend = (uint *) CFG_MEMTEST_END; 158 uint *p; 159 160 puts("SDRAM test phase 1:\n"); 161 for (p = pstart; p < pend; p++) 162 *p = 0xaaaaaaaa; 163 164 for (p = pstart; p < pend; p++) { 165 if (*p != 0xaaaaaaaa) { 166 printf("SDRAM test fails at: %08x\n", (uint) p); 167 return 1; 168 } 169 } 170 171 puts("SDRAM test phase 2:\n"); 172 for (p = pstart; p < pend; p++) 173 *p = 0x55555555; 174 175 for (p = pstart; p < pend; p++) { 176 if (*p != 0x55555555) { 177 printf("SDRAM test fails at: %08x\n", (uint) p); 178 return 1; 179 } 180 } 181 182 puts("SDRAM test passed.\n"); 183 return 0; 184 } 185 #endif 186 187 188 #if !defined(CONFIG_SPD_EEPROM) 189 /* 190 * Fixed sdram init -- doesn't use serial presence detect. 191 */ 192 193 long int fixed_sdram(void) 194 { 195 #if !defined(CFG_RAMBOOT) 196 volatile immap_t *immap = (immap_t *)CFG_IMMR; 197 volatile ccsr_ddr_t *ddr = &immap->im_ddr1; 198 uint d_init; 199 200 ddr->cs0_bnds = 0x0000001f; 201 ddr->cs0_config = 0x80010202; 202 203 ddr->ext_refrec = 0x00000000; 204 ddr->timing_cfg_0 = 0x00260802; 205 ddr->timing_cfg_1 = 0x3935d322; 206 ddr->timing_cfg_2 = 0x14904cc8; 207 ddr->sdram_mode_1 = 0x00480432; 208 ddr->sdram_mode_2 = 0x00000000; 209 ddr->sdram_interval = 0x06180fff; /* 0x06180100; */ 210 ddr->sdram_data_init = 0xDEADBEEF; 211 ddr->sdram_clk_cntl = 0x03800000; 212 ddr->sdram_cfg_2 = 0x04400010; 213 214 #if defined(CONFIG_DDR_ECC) 215 ddr->err_int_en = 0x0000000d; 216 ddr->err_disable = 0x00000000; 217 ddr->err_sbe = 0x00010000; 218 #endif 219 asm("sync;isync"); 220 221 udelay(500); 222 223 ddr->sdram_cfg_1 = 0xc3000000; /* 0xe3008000;*/ 224 225 226 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 227 d_init = 1; 228 debug("DDR - 1st controller: memory initializing\n"); 229 /* 230 * Poll until memory is initialized. 231 * 512 Meg at 400 might hit this 200 times or so. 232 */ 233 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) 234 udelay(1000); 235 236 debug("DDR: memory initialized\n\n"); 237 asm("sync; isync"); 238 udelay(500); 239 #endif 240 241 return 512 * 1024 * 1024; 242 #endif 243 return CFG_SDRAM_SIZE * 1024 * 1024; 244 } 245 246 #endif 247 248 #if defined(CONFIG_PCI) 249 /* 250 * Initialize PCI Devices, report devices found. 251 */ 252 253 #ifndef CONFIG_PCI_PNP 254 static struct pci_config_table pci_fsl86xxads_config_table[] = { 255 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 256 PCI_IDSEL_NUMBER, PCI_ANY_ID, 257 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, 258 PCI_ENET0_MEMADDR, 259 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} }, 260 {} 261 }; 262 #endif 263 264 265 static struct pci_controller pci1_hose = { 266 #ifndef CONFIG_PCI_PNP 267 config_table:pci_mpc86xxcts_config_table 268 #endif 269 }; 270 #endif /* CONFIG_PCI */ 271 272 #ifdef CONFIG_PCIE1 273 static struct pci_controller pcie1_hose; 274 #endif 275 276 #ifdef CONFIG_PCIE2 277 static struct pci_controller pcie2_hose; 278 #endif 279 280 int first_free_busno = 0; 281 282 void pci_init_board(void) 283 { 284 volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; 285 volatile ccsr_gur_t *gur = &immap->im_gur; 286 uint devdisr = gur->devdisr; 287 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 288 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; 289 290 printf( " pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", 291 devdisr, io_sel, host_agent); 292 293 294 #ifdef CONFIG_PCIE1 295 { 296 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; 297 extern void fsl_pci_init(struct pci_controller *hose); 298 struct pci_controller *hose = &pcie1_hose; 299 int pcie_configured = (io_sel == 1) || (io_sel == 4); 300 int pcie_ep = (host_agent == 0) || (host_agent == 2) || 301 (host_agent == 5); 302 303 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) { 304 printf(" PCIe 1 connected to Uli as %s (base address %x)\n", 305 pcie_ep ? "End Point" : "Root Complex", 306 (uint)pci); 307 if (pci->pme_msg_det) 308 pci->pme_msg_det = 0xffffffff; 309 310 /* inbound */ 311 pci_set_region(hose->regions + 0, 312 CFG_PCI_MEMORY_BUS, 313 CFG_PCI_MEMORY_PHYS, 314 CFG_PCI_MEMORY_SIZE, 315 PCI_REGION_MEM | PCI_REGION_MEMORY); 316 317 /* outbound memory */ 318 pci_set_region(hose->regions + 1, 319 CFG_PCIE1_MEM_BASE, 320 CFG_PCIE1_MEM_PHYS, 321 CFG_PCIE1_MEM_SIZE, 322 PCI_REGION_MEM); 323 324 /* outbound io */ 325 pci_set_region(hose->regions + 2, 326 CFG_PCIE1_IO_BASE, 327 CFG_PCIE1_IO_PHYS, 328 CFG_PCIE1_IO_SIZE, 329 PCI_REGION_IO); 330 331 hose->region_count = 3; 332 333 hose->first_busno = first_free_busno; 334 pci_setup_indirect(hose, (int)&pci->cfg_addr, 335 (int)&pci->cfg_data); 336 337 fsl_pci_init(hose); 338 339 first_free_busno = hose->last_busno + 1; 340 printf(" PCI-Express 1 on bus %02x - %02x\n", 341 hose->first_busno, hose->last_busno); 342 343 } else 344 puts(" PCI-Express 1: Disabled\n"); 345 } 346 #else 347 puts("PCI-Express 1: Disabled\n"); 348 #endif /* CONFIG_PCIE1 */ 349 350 351 #ifdef CONFIG_PCIE2 352 { 353 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR; 354 extern void fsl_pci_init(struct pci_controller *hose); 355 struct pci_controller *hose = &pcie2_hose; 356 357 int pcie_configured = (io_sel == 0) || (io_sel == 4); 358 int pcie_ep = (host_agent == 0) || (host_agent == 1) || 359 (host_agent == 4); 360 361 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)) { 362 printf(" PCI-Express 2 connected to slot as %s" \ 363 " (base address %x)\n", 364 pcie_ep ? "End Point" : "Root Complex", 365 (uint)pci); 366 if (pci->pme_msg_det) 367 pci->pme_msg_det = 0xffffffff; 368 369 /* inbound */ 370 pci_set_region(hose->regions + 0, 371 CFG_PCI_MEMORY_BUS, 372 CFG_PCI_MEMORY_PHYS, 373 CFG_PCI_MEMORY_SIZE, 374 PCI_REGION_MEM | PCI_REGION_MEMORY); 375 376 /* outbound memory */ 377 pci_set_region(hose->regions + 1, 378 CFG_PCIE2_MEM_BASE, 379 CFG_PCIE2_MEM_PHYS, 380 CFG_PCIE2_MEM_SIZE, 381 PCI_REGION_MEM); 382 383 /* outbound io */ 384 pci_set_region(hose->regions + 2, 385 CFG_PCIE2_IO_BASE, 386 CFG_PCIE2_IO_PHYS, 387 CFG_PCIE2_IO_SIZE, 388 PCI_REGION_IO); 389 390 hose->region_count = 3; 391 392 hose->first_busno = first_free_busno; 393 pci_setup_indirect(hose, (int)&pci->cfg_addr, 394 (int)&pci->cfg_data); 395 396 fsl_pci_init(hose); 397 398 first_free_busno = hose->last_busno + 1; 399 printf(" PCI-Express 2 on bus %02x - %02x\n", 400 hose->first_busno, hose->last_busno); 401 } else 402 puts(" PCI-Express 2: Disabled\n"); 403 } 404 #else 405 puts("PCI-Express 2: Disabled\n"); 406 #endif /* CONFIG_PCIE2 */ 407 408 409 #ifdef CONFIG_PCI1 410 { 411 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; 412 extern void fsl_pci_init(struct pci_controller *hose); 413 struct pci_controller *hose = &pci1_hose; 414 int pci_agent = (host_agent >= 4) && (host_agent <= 6); 415 416 if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) { 417 printf(" PCI connected to PCI slots as %s" \ 418 " (base address %x)\n", 419 pci_agent ? "Agent" : "Host", 420 (uint)pci); 421 422 /* inbound */ 423 pci_set_region(hose->regions + 0, 424 CFG_PCI_MEMORY_BUS, 425 CFG_PCI_MEMORY_PHYS, 426 CFG_PCI_MEMORY_SIZE, 427 PCI_REGION_MEM | PCI_REGION_MEMORY); 428 429 /* outbound memory */ 430 pci_set_region(hose->regions + 1, 431 CFG_PCI1_MEM_BASE, 432 CFG_PCI1_MEM_PHYS, 433 CFG_PCI1_MEM_SIZE, 434 PCI_REGION_MEM); 435 436 /* outbound io */ 437 pci_set_region(hose->regions + 2, 438 CFG_PCI1_IO_BASE, 439 CFG_PCI1_IO_PHYS, 440 CFG_PCI1_IO_SIZE, 441 PCI_REGION_IO); 442 443 hose->region_count = 3; 444 445 hose->first_busno = first_free_busno; 446 pci_setup_indirect(hose, (int) &pci->cfg_addr, 447 (int) &pci->cfg_data); 448 449 fsl_pci_init(hose); 450 451 first_free_busno = hose->last_busno + 1; 452 printf(" PCI on bus %02x - %02x\n", 453 hose->first_busno, hose->last_busno); 454 455 456 } else 457 puts(" PCI: Disabled\n"); 458 } 459 #endif /* CONFIG_PCI1 */ 460 } 461 462 #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) 463 void 464 ft_board_setup(void *blob, bd_t *bd) 465 { 466 u32 *p; 467 int len; 468 469 ft_cpu_setup(blob, bd); 470 471 p = ft_get_prop(blob, "/memory/reg", &len); 472 if (p != NULL) { 473 *p++ = cpu_to_be32(bd->bi_memstart); 474 *p = cpu_to_be32(bd->bi_memsize); 475 } 476 477 #ifdef CONFIG_PCI1 478 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len); 479 if (p != NULL) { 480 p[0] = 0; 481 p[1] = pci1_hose.last_busno - pci1_hose.first_busno; 482 debug("pci@8000 first_busno=%d last_busno=%d\n",p[0],p[1]); 483 } 484 #endif 485 #ifdef CONFIG_PCIE1 486 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len); 487 if (p != NULL) { 488 p[0] = 0; 489 p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; 490 debug("pcie@9000 first_busno=%d last_busno=%d\n",p[0],p[1]); 491 } 492 #endif 493 #ifdef CONFIG_PCIE2 494 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len); 495 if (p != NULL) { 496 p[0] = 0; 497 p[1] = pcie2_hose.last_busno - pcie2_hose.first_busno; 498 debug("pcie@9000 first_busno=%d last_busno=%d\n",p[0],p[1]); 499 } 500 #endif 501 502 } 503 #endif 504 505 /* 506 * get_board_sys_clk 507 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ 508 */ 509 510 unsigned long 511 get_board_sys_clk(ulong dummy) 512 { 513 u8 i; 514 ulong val = 0; 515 ulong a; 516 517 a = PIXIS_BASE + PIXIS_SPD; 518 i = in8(a); 519 i &= 0x07; 520 521 switch (i) { 522 case 0: 523 val = 33333000; 524 break; 525 case 1: 526 val = 39999600; 527 break; 528 case 2: 529 val = 49999500; 530 break; 531 case 3: 532 val = 66666000; 533 break; 534 case 4: 535 val = 83332500; 536 break; 537 case 5: 538 val = 99999000; 539 break; 540 case 6: 541 val = 133332000; 542 break; 543 case 7: 544 val = 166665000; 545 break; 546 } 547 548 return val; 549 } 550