1 /* 2 * Copyright 2007-2008 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/mmu.h> 28 #include <asm/cache.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/io.h> 33 #include <miiphy.h> 34 #include <libfdt.h> 35 #include <fdt_support.h> 36 #include <tsec.h> 37 38 #include "../common/pixis.h" 39 #include "../common/sgmii_riser.h" 40 41 long int fixed_sdram(void); 42 43 int checkboard (void) 44 { 45 u8 vboot; 46 u8 *pixis_base = (u8 *)PIXIS_BASE; 47 48 puts ("Board: MPC8572DS "); 49 #ifdef CONFIG_PHYS_64BIT 50 puts ("(36-bit addrmap) "); 51 #endif 52 printf ("Sys ID: 0x%02x, " 53 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 54 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 55 in_8(pixis_base + PIXIS_PVER)); 56 57 vboot = in_8(pixis_base + PIXIS_VBOOT); 58 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) { 59 case PIXIS_VBOOT_LBMAP_NOR0: 60 puts ("vBank: 0\n"); 61 break; 62 case PIXIS_VBOOT_LBMAP_PJET: 63 puts ("Promjet\n"); 64 break; 65 case PIXIS_VBOOT_LBMAP_NAND: 66 puts ("NAND\n"); 67 break; 68 case PIXIS_VBOOT_LBMAP_NOR1: 69 puts ("vBank: 1\n"); 70 break; 71 } 72 73 return 0; 74 } 75 76 phys_size_t initdram(int board_type) 77 { 78 phys_size_t dram_size = 0; 79 80 puts("Initializing...."); 81 82 #ifdef CONFIG_SPD_EEPROM 83 dram_size = fsl_ddr_sdram(); 84 #else 85 dram_size = fixed_sdram(); 86 #endif 87 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 88 dram_size *= 0x100000; 89 90 puts(" DDR: "); 91 return dram_size; 92 } 93 94 #if !defined(CONFIG_SPD_EEPROM) 95 /* 96 * Fixed sdram init -- doesn't use serial presence detect. 97 */ 98 99 phys_size_t fixed_sdram (void) 100 { 101 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 102 volatile ccsr_ddr_t *ddr= &immap->im_ddr; 103 uint d_init; 104 105 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 106 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 107 108 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 109 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 110 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 111 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 112 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 113 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 114 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 115 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 116 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 117 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 118 119 #if defined (CONFIG_DDR_ECC) 120 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; 121 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; 122 ddr->err_sbe = CONFIG_SYS_DDR_SBE; 123 #endif 124 asm("sync;isync"); 125 126 udelay(500); 127 128 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 129 130 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 131 d_init = 1; 132 debug("DDR - 1st controller: memory initializing\n"); 133 /* 134 * Poll until memory is initialized. 135 * 512 Meg at 400 might hit this 200 times or so. 136 */ 137 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 138 udelay(1000); 139 } 140 debug("DDR: memory initialized\n\n"); 141 asm("sync; isync"); 142 udelay(500); 143 #endif 144 145 return 512 * 1024 * 1024; 146 } 147 148 #endif 149 150 #ifdef CONFIG_PCIE1 151 static struct pci_controller pcie1_hose; 152 #endif 153 154 #ifdef CONFIG_PCIE2 155 static struct pci_controller pcie2_hose; 156 #endif 157 158 #ifdef CONFIG_PCIE3 159 static struct pci_controller pcie3_hose; 160 #endif 161 162 int first_free_busno=0; 163 #ifdef CONFIG_PCI 164 void pci_init_board(void) 165 { 166 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 167 uint devdisr = gur->devdisr; 168 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 169 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; 170 171 debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", 172 devdisr, io_sel, host_agent); 173 174 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) 175 printf (" eTSEC1 is in sgmii mode.\n"); 176 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) 177 printf (" eTSEC2 is in sgmii mode.\n"); 178 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) 179 printf (" eTSEC3 is in sgmii mode.\n"); 180 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS)) 181 printf (" eTSEC4 is in sgmii mode.\n"); 182 183 184 #ifdef CONFIG_PCIE3 185 { 186 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; 187 struct pci_controller *hose = &pcie3_hose; 188 int pcie_ep = (host_agent == 0) || (host_agent == 3) || 189 (host_agent == 5) || (host_agent == 6); 190 int pcie_configured = (io_sel == 0x7); 191 struct pci_region *r = hose->regions; 192 u32 temp32; 193 194 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ 195 printf ("\n PCIE3 connected to ULI as %s (base address %x)", 196 pcie_ep ? "End Point" : "Root Complex", 197 (uint)pci); 198 if (pci->pme_msg_det) { 199 pci->pme_msg_det = 0xffffffff; 200 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 201 } 202 printf ("\n"); 203 204 /* outbound memory */ 205 pci_set_region(r++, 206 CONFIG_SYS_PCIE3_MEM_BUS, 207 CONFIG_SYS_PCIE3_MEM_PHYS, 208 CONFIG_SYS_PCIE3_MEM_SIZE, 209 PCI_REGION_MEM); 210 211 /* outbound io */ 212 pci_set_region(r++, 213 CONFIG_SYS_PCIE3_IO_BUS, 214 CONFIG_SYS_PCIE3_IO_PHYS, 215 CONFIG_SYS_PCIE3_IO_SIZE, 216 PCI_REGION_IO); 217 218 hose->region_count = r - hose->regions; 219 hose->first_busno=first_free_busno; 220 221 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 222 223 first_free_busno=hose->last_busno+1; 224 printf (" PCIE3 on bus %02x - %02x\n", 225 hose->first_busno,hose->last_busno); 226 227 /* 228 * Activate ULI1575 legacy chip by performing a fake 229 * memory access. Needed to make ULI RTC work. 230 * Device 1d has the first on-board memory BAR. 231 */ 232 233 pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ), 234 PCI_BASE_ADDRESS_1, &temp32); 235 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) { 236 void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0), 237 temp32, 4, 0); 238 debug(" uli1572 read to %p\n", p); 239 in_be32(p); 240 } 241 } else { 242 printf (" PCIE3: disabled\n"); 243 } 244 245 } 246 #else 247 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ 248 #endif 249 250 #ifdef CONFIG_PCIE2 251 { 252 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; 253 struct pci_controller *hose = &pcie2_hose; 254 int pcie_ep = (host_agent == 2) || (host_agent == 4) || 255 (host_agent == 6) || (host_agent == 0); 256 int pcie_configured = (io_sel == 0x3) || (io_sel == 0x7); 257 struct pci_region *r = hose->regions; 258 259 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ 260 printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)", 261 pcie_ep ? "End Point" : "Root Complex", 262 (uint)pci); 263 if (pci->pme_msg_det) { 264 pci->pme_msg_det = 0xffffffff; 265 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 266 } 267 printf ("\n"); 268 269 /* outbound memory */ 270 pci_set_region(r++, 271 CONFIG_SYS_PCIE2_MEM_BUS, 272 CONFIG_SYS_PCIE2_MEM_PHYS, 273 CONFIG_SYS_PCIE2_MEM_SIZE, 274 PCI_REGION_MEM); 275 276 /* outbound io */ 277 pci_set_region(r++, 278 CONFIG_SYS_PCIE2_IO_BUS, 279 CONFIG_SYS_PCIE2_IO_PHYS, 280 CONFIG_SYS_PCIE2_IO_SIZE, 281 PCI_REGION_IO); 282 283 hose->region_count = r - hose->regions; 284 hose->first_busno=first_free_busno; 285 286 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 287 first_free_busno=hose->last_busno+1; 288 printf (" PCIE2 on bus %02x - %02x\n", 289 hose->first_busno,hose->last_busno); 290 291 } else { 292 printf (" PCIE2: disabled\n"); 293 } 294 295 } 296 #else 297 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ 298 #endif 299 #ifdef CONFIG_PCIE1 300 { 301 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; 302 struct pci_controller *hose = &pcie1_hose; 303 int pcie_ep = (host_agent <= 1) || (host_agent == 4) || 304 (host_agent == 5); 305 int pcie_configured = (io_sel == 0x2) || (io_sel == 0x3) || 306 (io_sel == 0x7) || (io_sel == 0xb) || 307 (io_sel == 0xc) || (io_sel == 0xf); 308 struct pci_region *r = hose->regions; 309 310 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 311 printf ("\n PCIE1 connected to Slot 2 as %s (base address %x)", 312 pcie_ep ? "End Point" : "Root Complex", 313 (uint)pci); 314 if (pci->pme_msg_det) { 315 pci->pme_msg_det = 0xffffffff; 316 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 317 } 318 printf ("\n"); 319 320 /* outbound memory */ 321 pci_set_region(r++, 322 CONFIG_SYS_PCIE1_MEM_BUS, 323 CONFIG_SYS_PCIE1_MEM_PHYS, 324 CONFIG_SYS_PCIE1_MEM_SIZE, 325 PCI_REGION_MEM); 326 327 /* outbound io */ 328 pci_set_region(r++, 329 CONFIG_SYS_PCIE1_IO_BUS, 330 CONFIG_SYS_PCIE1_IO_PHYS, 331 CONFIG_SYS_PCIE1_IO_SIZE, 332 PCI_REGION_IO); 333 334 hose->region_count = r - hose->regions; 335 hose->first_busno=first_free_busno; 336 337 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 338 339 first_free_busno=hose->last_busno+1; 340 printf(" PCIE1 on bus %02x - %02x\n", 341 hose->first_busno,hose->last_busno); 342 343 } else { 344 printf (" PCIE1: disabled\n"); 345 } 346 347 } 348 #else 349 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 350 #endif 351 } 352 #endif 353 354 int board_early_init_r(void) 355 { 356 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 357 const u8 flash_esel = 2; 358 359 /* 360 * Remap Boot flash + PROMJET region to caching-inhibited 361 * so that flash can be erased properly. 362 */ 363 364 /* Flush d-cache and invalidate i-cache of any FLASH data */ 365 flush_dcache(); 366 invalidate_icache(); 367 368 /* invalidate existing TLB entry for flash + promjet */ 369 disable_tlb(flash_esel); 370 371 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 372 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 373 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 374 375 return 0; 376 } 377 378 #ifdef CONFIG_GET_CLK_FROM_ICS307 379 /* decode S[0-2] to Output Divider (OD) */ 380 static unsigned char ics307_S_to_OD[] = { 381 10, 2, 8, 4, 5, 7, 3, 6 382 }; 383 384 /* Calculate frequency being generated by ICS307-02 clock chip based upon 385 * the control bytes being programmed into it. */ 386 /* XXX: This function should probably go into a common library */ 387 static unsigned long 388 ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2) 389 { 390 const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ; 391 unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); 392 unsigned long RDW = cw2 & 0x7F; 393 unsigned long OD = ics307_S_to_OD[cw0 & 0x7]; 394 unsigned long freq; 395 396 /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */ 397 398 /* cw0: C1 C0 TTL F1 F0 S2 S1 S0 399 * cw1: V8 V7 V6 V5 V4 V3 V2 V1 400 * cw2: V0 R6 R5 R4 R3 R2 R1 R0 401 * 402 * R6:R0 = Reference Divider Word (RDW) 403 * V8:V0 = VCO Divider Word (VDW) 404 * S2:S0 = Output Divider Select (OD) 405 * F1:F0 = Function of CLK2 Output 406 * TTL = duty cycle 407 * C1:C0 = internal load capacitance for cyrstal 408 */ 409 410 /* Adding 1 to get a "nicely" rounded number, but this needs 411 * more tweaking to get a "properly" rounded number. */ 412 413 freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)); 414 415 debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2, 416 freq); 417 return freq; 418 } 419 420 unsigned long get_board_sys_clk(ulong dummy) 421 { 422 u8 *pixis_base = (u8 *)PIXIS_BASE; 423 424 return ics307_clk_freq ( 425 in_8(pixis_base + PIXIS_VSYSCLK0), 426 in_8(pixis_base + PIXIS_VSYSCLK1), 427 in_8(pixis_base + PIXIS_VSYSCLK2) 428 ); 429 } 430 431 unsigned long get_board_ddr_clk(ulong dummy) 432 { 433 u8 *pixis_base = (u8 *)PIXIS_BASE; 434 435 return ics307_clk_freq ( 436 in_8(pixis_base + PIXIS_VDDRCLK0), 437 in_8(pixis_base + PIXIS_VDDRCLK1), 438 in_8(pixis_base + PIXIS_VDDRCLK2) 439 ); 440 } 441 #else 442 unsigned long get_board_sys_clk(ulong dummy) 443 { 444 u8 i; 445 ulong val = 0; 446 u8 *pixis_base = (u8 *)PIXIS_BASE; 447 448 i = in_8(pixis_base + PIXIS_SPD); 449 i &= 0x07; 450 451 switch (i) { 452 case 0: 453 val = 33333333; 454 break; 455 case 1: 456 val = 40000000; 457 break; 458 case 2: 459 val = 50000000; 460 break; 461 case 3: 462 val = 66666666; 463 break; 464 case 4: 465 val = 83333333; 466 break; 467 case 5: 468 val = 100000000; 469 break; 470 case 6: 471 val = 133333333; 472 break; 473 case 7: 474 val = 166666666; 475 break; 476 } 477 478 return val; 479 } 480 481 unsigned long get_board_ddr_clk(ulong dummy) 482 { 483 u8 i; 484 ulong val = 0; 485 u8 *pixis_base = (u8 *)PIXIS_BASE; 486 487 i = in_8(pixis_base + PIXIS_SPD); 488 i &= 0x38; 489 i >>= 3; 490 491 switch (i) { 492 case 0: 493 val = 33333333; 494 break; 495 case 1: 496 val = 40000000; 497 break; 498 case 2: 499 val = 50000000; 500 break; 501 case 3: 502 val = 66666666; 503 break; 504 case 4: 505 val = 83333333; 506 break; 507 case 5: 508 val = 100000000; 509 break; 510 case 6: 511 val = 133333333; 512 break; 513 case 7: 514 val = 166666666; 515 break; 516 } 517 return val; 518 } 519 #endif 520 521 #ifdef CONFIG_TSEC_ENET 522 int board_eth_init(bd_t *bis) 523 { 524 struct tsec_info_struct tsec_info[4]; 525 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 526 int num = 0; 527 528 #ifdef CONFIG_TSEC1 529 SET_STD_TSEC_INFO(tsec_info[num], 1); 530 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) 531 tsec_info[num].flags |= TSEC_SGMII; 532 num++; 533 #endif 534 #ifdef CONFIG_TSEC2 535 SET_STD_TSEC_INFO(tsec_info[num], 2); 536 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) 537 tsec_info[num].flags |= TSEC_SGMII; 538 num++; 539 #endif 540 #ifdef CONFIG_TSEC3 541 SET_STD_TSEC_INFO(tsec_info[num], 3); 542 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) 543 tsec_info[num].flags |= TSEC_SGMII; 544 num++; 545 #endif 546 #ifdef CONFIG_TSEC4 547 SET_STD_TSEC_INFO(tsec_info[num], 4); 548 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS)) 549 tsec_info[num].flags |= TSEC_SGMII; 550 num++; 551 #endif 552 553 if (!num) { 554 printf("No TSECs initialized\n"); 555 556 return 0; 557 } 558 559 #ifdef CONFIG_FSL_SGMII_RISER 560 fsl_sgmii_riser_init(tsec_info, num); 561 #endif 562 563 tsec_eth_init(bis, tsec_info, num); 564 565 return 0; 566 } 567 #endif 568 569 #if defined(CONFIG_OF_BOARD_SETUP) 570 void ft_board_setup(void *blob, bd_t *bd) 571 { 572 phys_addr_t base; 573 phys_size_t size; 574 575 ft_cpu_setup(blob, bd); 576 577 base = getenv_bootm_low(); 578 size = getenv_bootm_size(); 579 580 fdt_fixup_memory(blob, (u64)base, (u64)size); 581 582 #ifdef CONFIG_PCIE3 583 ft_fsl_pci_setup(blob, "pci0", &pcie3_hose); 584 #endif 585 #ifdef CONFIG_PCIE2 586 ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); 587 #endif 588 #ifdef CONFIG_PCIE1 589 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); 590 #endif 591 #ifdef CONFIG_FSL_SGMII_RISER 592 fsl_sgmii_riser_fdt_fixup(blob); 593 #endif 594 } 595 #endif 596 597 #ifdef CONFIG_MP 598 extern void cpu_mp_lmb_reserve(struct lmb *lmb); 599 600 void board_lmb_reserve(struct lmb *lmb) 601 { 602 cpu_mp_lmb_reserve(lmb); 603 } 604 #endif 605