1 /* 2 * Copyright 2009 Freescale Semiconductor. 3 * 4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <pci.h> 27 #include <asm/processor.h> 28 #include <asm/mmu.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/io.h> 33 #include <spd_sdram.h> 34 #include <i2c.h> 35 #include <ioports.h> 36 #include <libfdt.h> 37 #include <fdt_support.h> 38 39 #include "bcsr.h" 40 41 phys_size_t fixed_sdram(void); 42 43 const qe_iop_conf_t qe_iop_conf_tab[] = { 44 /* QE_MUX_MDC */ 45 {2, 31, 1, 0, 1}, /* QE_MUX_MDC */ 46 47 /* QE_MUX_MDIO */ 48 {2, 30, 3, 0, 2}, /* QE_MUX_MDIO */ 49 50 /* UCC_1_RGMII */ 51 {2, 11, 2, 0, 1}, /* CLK12 */ 52 {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */ 53 {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */ 54 {0, 2, 1, 0, 1}, /* ENET1_TXD2_SER1_TXD2 */ 55 {0, 3, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */ 56 {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */ 57 {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */ 58 {0, 8, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */ 59 {0, 9, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */ 60 {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */ 61 {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */ 62 {2, 8, 2, 0, 1}, /* ENET1_GRXCLK */ 63 {2, 20, 1, 0, 2}, /* ENET1_GTXCLK */ 64 65 /* UCC_2_RGMII */ 66 {2, 16, 2, 0, 3}, /* CLK17 */ 67 {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */ 68 {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */ 69 {0, 16, 1, 0, 1}, /* ENET2_TXD2_SER2_TXD2 */ 70 {0, 17, 1, 0, 1}, /* ENET2_TXD3_SER2_TXD3 */ 71 {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */ 72 {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */ 73 {0, 22, 2, 0, 1}, /* ENET2_RXD2_SER2_RXD2 */ 74 {0, 23, 2, 0, 1}, /* ENET2_RXD3_SER2_RXD3 */ 75 {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */ 76 {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */ 77 {2, 3, 2, 0, 1}, /* ENET2_GRXCLK */ 78 {2, 2, 1, 0, 2}, /* ENET2_GTXCLK */ 79 80 /* UCC_3_RGMII */ 81 {2, 11, 2, 0, 1}, /* CLK12 */ 82 {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */ 83 {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */ 84 {0, 31, 1, 0, 2}, /* ENET3_TXD2_SER3_TXD2 */ 85 {1, 0, 1, 0, 3}, /* ENET3_TXD3_SER3_TXD3 */ 86 {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */ 87 {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */ 88 {1, 5, 2, 0, 2}, /* ENET3_RXD2_SER3_RXD2 */ 89 {1, 6, 2, 0, 3}, /* ENET3_RXD3_SER3_RXD3 */ 90 {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */ 91 {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */ 92 {2, 9, 2, 0, 2}, /* ENET3_GRXCLK */ 93 {2, 25, 1, 0, 2}, /* ENET3_GTXCLK */ 94 95 /* UCC_4_RGMII */ 96 {2, 16, 2, 0, 3}, /* CLK17 */ 97 {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */ 98 {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */ 99 {1, 14, 1, 0, 1}, /* ENET4_TXD2_SER4_TXD2 */ 100 {1, 15, 1, 0, 2}, /* ENET4_TXD3_SER4_TXD3 */ 101 {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */ 102 {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */ 103 {1, 20, 2, 0, 1}, /* ENET4_RXD2_SER4_RXD2 */ 104 {1, 21, 2, 0, 2}, /* ENET4_RXD3_SER4_RXD3 */ 105 {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */ 106 {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */ 107 {2, 17, 2, 0, 2}, /* ENET4_GRXCLK */ 108 {2, 24, 1, 0, 2}, /* ENET4_GTXCLK */ 109 110 /* UART1 is muxed with QE PortF bit [9-12].*/ 111 {5, 12, 2, 0, 3}, /* UART1_SIN */ 112 {5, 9, 1, 0, 3}, /* UART1_SOUT */ 113 {5, 10, 2, 0, 3}, /* UART1_CTS_B */ 114 {5, 11, 1, 0, 2}, /* UART1_RTS_B */ 115 116 {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */ 117 }; 118 119 void local_bus_init(void); 120 121 int board_early_init_f (void) 122 { 123 /* 124 * Initialize local bus. 125 */ 126 local_bus_init (); 127 128 enable_8569mds_flash_write(); 129 130 #ifdef CONFIG_QE 131 enable_8569mds_qe_mdio(); 132 #endif 133 134 #if CONFIG_SYS_I2C2_OFFSET 135 /* Enable I2C2 signals instead of SD signals */ 136 volatile struct ccsr_gur *gur; 137 gur = (struct ccsr_gur *)(CONFIG_SYS_IMMR + 0xe0000); 138 gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK; 139 gur->plppar1 |= PLPPAR1_I2C2_VAL; 140 gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK; 141 gur->plpdir1 |= PLPDIR1_I2C2_VAL; 142 143 disable_8569mds_brd_eeprom_write_protect(); 144 #endif 145 146 return 0; 147 } 148 149 int checkboard (void) 150 { 151 printf ("Board: 8569 MDS\n"); 152 153 return 0; 154 } 155 156 phys_size_t 157 initdram(int board_type) 158 { 159 long dram_size = 0; 160 161 puts("Initializing\n"); 162 163 #if defined(CONFIG_DDR_DLL) 164 /* 165 * Work around to stabilize DDR DLL MSYNC_IN. 166 * Errata DDR9 seems to have been fixed. 167 * This is now the workaround for Errata DDR11: 168 * Override DLL = 1, Course Adj = 1, Tap Select = 0 169 */ 170 volatile ccsr_gur_t *gur = 171 (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 172 173 out_be32(&gur->ddrdllcr, 0x81000000); 174 udelay(200); 175 #endif 176 177 #ifdef CONFIG_SPD_EEPROM 178 dram_size = fsl_ddr_sdram(); 179 #else 180 dram_size = fixed_sdram(); 181 #endif 182 183 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 184 dram_size *= 0x100000; 185 186 puts(" DDR: "); 187 return dram_size; 188 } 189 190 #if !defined(CONFIG_SPD_EEPROM) 191 phys_size_t fixed_sdram(void) 192 { 193 volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; 194 uint d_init; 195 196 out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); 197 out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); 198 out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); 199 out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); 200 out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); 201 out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); 202 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); 203 out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2); 204 out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE); 205 out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2); 206 out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL); 207 out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); 208 out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); 209 out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); 210 out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); 211 out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL); 212 out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL); 213 out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2); 214 #if defined (CONFIG_DDR_ECC) 215 out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN); 216 out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS); 217 out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE); 218 #endif 219 udelay(500); 220 221 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); 222 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 223 d_init = 1; 224 debug("DDR - 1st controller: memory initializing\n"); 225 /* 226 * Poll until memory is initialized. 227 * 512 Meg at 400 might hit this 200 times or so. 228 */ 229 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 230 udelay(1000); 231 } 232 debug("DDR: memory initialized\n\n"); 233 udelay(500); 234 #endif 235 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 236 } 237 #endif 238 239 /* 240 * Initialize Local Bus 241 */ 242 void 243 local_bus_init(void) 244 { 245 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 246 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); 247 248 uint clkdiv; 249 uint lbc_hz; 250 sys_info_t sysinfo; 251 252 get_sys_info(&sysinfo); 253 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; 254 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; 255 256 out_be32(&gur->lbiuiplldcr1, 0x00078080); 257 if (clkdiv == 16) 258 out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0); 259 else if (clkdiv == 8) 260 out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0); 261 else if (clkdiv == 4) 262 out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0); 263 264 out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000); 265 } 266 267 #ifdef CONFIG_PCIE1 268 static struct pci_controller pcie1_hose; 269 #endif /* CONFIG_PCIE1 */ 270 271 int first_free_busno = 0; 272 273 #ifdef CONFIG_PCI 274 void 275 pci_init_board(void) 276 { 277 volatile ccsr_gur_t *gur; 278 uint io_sel; 279 uint host_agent; 280 281 gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 282 io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 283 host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; 284 285 #ifdef CONFIG_PCIE1 286 { 287 volatile ccsr_fsl_pci_t *pci; 288 struct pci_controller *hose; 289 int pcie_ep; 290 struct pci_region *r; 291 int pcie_configured; 292 293 pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; 294 hose = &pcie1_hose; 295 pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); 296 r = hose->regions; 297 pcie_configured = io_sel >= 1; 298 299 if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ 300 printf ("\n PCIE connected to slot as %s (base address %x)", 301 pcie_ep ? "End Point" : "Root Complex", 302 (uint)pci); 303 304 if (pci->pme_msg_det) { 305 pci->pme_msg_det = 0xffffffff; 306 debug (" with errors. Clearing. Now 0x%08x", 307 pci->pme_msg_det); 308 } 309 printf ("\n"); 310 311 /* inbound */ 312 r += fsl_pci_setup_inbound_windows(r); 313 314 /* outbound memory */ 315 pci_set_region(r++, 316 CONFIG_SYS_PCIE1_MEM_BUS, 317 CONFIG_SYS_PCIE1_MEM_PHYS, 318 CONFIG_SYS_PCIE1_MEM_SIZE, 319 PCI_REGION_MEM); 320 321 /* outbound io */ 322 pci_set_region(r++, 323 CONFIG_SYS_PCIE1_IO_BUS, 324 CONFIG_SYS_PCIE1_IO_PHYS, 325 CONFIG_SYS_PCIE1_IO_SIZE, 326 PCI_REGION_IO); 327 328 hose->region_count = r - hose->regions; 329 330 hose->first_busno=first_free_busno; 331 pci_setup_indirect(hose, (int) &pci->cfg_addr, 332 (int) &pci->cfg_data); 333 334 fsl_pci_init(hose); 335 printf ("PCIE on bus %02x - %02x\n", 336 hose->first_busno,hose->last_busno); 337 338 first_free_busno=hose->last_busno+1; 339 340 } else { 341 printf (" PCIE: disabled\n"); 342 } 343 } 344 #else 345 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 346 #endif 347 } 348 #endif /* CONFIG_PCI */ 349 350 #if defined(CONFIG_OF_BOARD_SETUP) 351 void ft_board_setup(void *blob, bd_t *bd) 352 { 353 ft_cpu_setup(blob, bd); 354 355 #ifdef CONFIG_PCIE1 356 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); 357 #endif 358 } 359 #endif 360