1*765547dcSHaiying Wang /* 2*765547dcSHaiying Wang * Copyright 2009 Freescale Semiconductor, Inc. 3*765547dcSHaiying Wang * 4*765547dcSHaiying Wang * This program is free software; you can redistribute it and/or 5*765547dcSHaiying Wang * modify it under the terms of the GNU General Public License 6*765547dcSHaiying Wang * Version 2 as published by the Free Software Foundation. 7*765547dcSHaiying Wang */ 8*765547dcSHaiying Wang 9*765547dcSHaiying Wang #include <common.h> 10*765547dcSHaiying Wang #include <i2c.h> 11*765547dcSHaiying Wang 12*765547dcSHaiying Wang #include <asm/fsl_ddr_sdram.h> 13*765547dcSHaiying Wang #include <asm/fsl_ddr_dimm_params.h> 14*765547dcSHaiying Wang 15*765547dcSHaiying Wang static void 16*765547dcSHaiying Wang get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address) 17*765547dcSHaiying Wang { 18*765547dcSHaiying Wang i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t)); 19*765547dcSHaiying Wang } 20*765547dcSHaiying Wang 21*765547dcSHaiying Wang 22*765547dcSHaiying Wang unsigned int fsl_ddr_get_mem_data_rate(void) 23*765547dcSHaiying Wang { 24*765547dcSHaiying Wang return get_ddr_freq(0); 25*765547dcSHaiying Wang } 26*765547dcSHaiying Wang 27*765547dcSHaiying Wang void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, 28*765547dcSHaiying Wang unsigned int ctrl_num) 29*765547dcSHaiying Wang { 30*765547dcSHaiying Wang unsigned int i; 31*765547dcSHaiying Wang unsigned int i2c_address = 0; 32*765547dcSHaiying Wang 33*765547dcSHaiying Wang for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { 34*765547dcSHaiying Wang if (ctrl_num == 0 && i == 0) 35*765547dcSHaiying Wang i2c_address = SPD_EEPROM_ADDRESS1; 36*765547dcSHaiying Wang if (ctrl_num == 0 && i == 1) 37*765547dcSHaiying Wang i2c_address = SPD_EEPROM_ADDRESS2; 38*765547dcSHaiying Wang get_spd(&(ctrl_dimms_spd[i]), i2c_address); 39*765547dcSHaiying Wang } 40*765547dcSHaiying Wang } 41*765547dcSHaiying Wang 42*765547dcSHaiying Wang void fsl_ddr_board_options(memctl_options_t *popts, 43*765547dcSHaiying Wang dimm_params_t *pdimm, 44*765547dcSHaiying Wang unsigned int ctrl_num) 45*765547dcSHaiying Wang { 46*765547dcSHaiying Wang /* 47*765547dcSHaiying Wang * Factors to consider for clock adjust: 48*765547dcSHaiying Wang * - number of chips on bus 49*765547dcSHaiying Wang * - position of slot 50*765547dcSHaiying Wang * - DDR1 vs. DDR2? 51*765547dcSHaiying Wang * - ??? 52*765547dcSHaiying Wang * 53*765547dcSHaiying Wang * This needs to be determined on a board-by-board basis. 54*765547dcSHaiying Wang * 0110 3/4 cycle late 55*765547dcSHaiying Wang * 0111 7/8 cycle late 56*765547dcSHaiying Wang */ 57*765547dcSHaiying Wang popts->clk_adjust = 6; 58*765547dcSHaiying Wang 59*765547dcSHaiying Wang /* 60*765547dcSHaiying Wang * Factors to consider for CPO: 61*765547dcSHaiying Wang * - frequency 62*765547dcSHaiying Wang * - ddr1 vs. ddr2 63*765547dcSHaiying Wang */ 64*765547dcSHaiying Wang popts->cpo_override = 0xff; 65*765547dcSHaiying Wang 66*765547dcSHaiying Wang /* 67*765547dcSHaiying Wang * Factors to consider for write data delay: 68*765547dcSHaiying Wang * - number of DIMMs 69*765547dcSHaiying Wang * 70*765547dcSHaiying Wang * 1 = 1/4 clock delay 71*765547dcSHaiying Wang * 2 = 1/2 clock delay 72*765547dcSHaiying Wang * 3 = 3/4 clock delay 73*765547dcSHaiying Wang * 4 = 1 clock delay 74*765547dcSHaiying Wang * 5 = 5/4 clock delay 75*765547dcSHaiying Wang * 6 = 3/2 clock delay 76*765547dcSHaiying Wang */ 77*765547dcSHaiying Wang popts->write_data_delay = 2; 78*765547dcSHaiying Wang 79*765547dcSHaiying Wang /* 80*765547dcSHaiying Wang * Factors to consider for half-strength driver enable: 81*765547dcSHaiying Wang * - number of DIMMs installed 82*765547dcSHaiying Wang */ 83*765547dcSHaiying Wang popts->half_strength_driver_enable = 0; 84*765547dcSHaiying Wang } 85