1 /* 2 * Copyright 2007 Freescale Semiconductor. 3 * 4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <pci.h> 27 #include <asm/processor.h> 28 #include <asm/immap_85xx.h> 29 #include <asm/immap_fsl_pci.h> 30 #include <spd.h> 31 #include <i2c.h> 32 #include <ioports.h> 33 #include <libfdt.h> 34 #include <fdt_support.h> 35 36 #include "bcsr.h" 37 38 const qe_iop_conf_t qe_iop_conf_tab[] = { 39 /* GETH1 */ 40 {4, 10, 1, 0, 2}, /* TxD0 */ 41 {4, 9, 1, 0, 2}, /* TxD1 */ 42 {4, 8, 1, 0, 2}, /* TxD2 */ 43 {4, 7, 1, 0, 2}, /* TxD3 */ 44 {4, 23, 1, 0, 2}, /* TxD4 */ 45 {4, 22, 1, 0, 2}, /* TxD5 */ 46 {4, 21, 1, 0, 2}, /* TxD6 */ 47 {4, 20, 1, 0, 2}, /* TxD7 */ 48 {4, 15, 2, 0, 2}, /* RxD0 */ 49 {4, 14, 2, 0, 2}, /* RxD1 */ 50 {4, 13, 2, 0, 2}, /* RxD2 */ 51 {4, 12, 2, 0, 2}, /* RxD3 */ 52 {4, 29, 2, 0, 2}, /* RxD4 */ 53 {4, 28, 2, 0, 2}, /* RxD5 */ 54 {4, 27, 2, 0, 2}, /* RxD6 */ 55 {4, 26, 2, 0, 2}, /* RxD7 */ 56 {4, 11, 1, 0, 2}, /* TX_EN */ 57 {4, 24, 1, 0, 2}, /* TX_ER */ 58 {4, 16, 2, 0, 2}, /* RX_DV */ 59 {4, 30, 2, 0, 2}, /* RX_ER */ 60 {4, 17, 2, 0, 2}, /* RX_CLK */ 61 {4, 19, 1, 0, 2}, /* GTX_CLK */ 62 {1, 31, 2, 0, 3}, /* GTX125 */ 63 64 /* GETH2 */ 65 {5, 10, 1, 0, 2}, /* TxD0 */ 66 {5, 9, 1, 0, 2}, /* TxD1 */ 67 {5, 8, 1, 0, 2}, /* TxD2 */ 68 {5, 7, 1, 0, 2}, /* TxD3 */ 69 {5, 23, 1, 0, 2}, /* TxD4 */ 70 {5, 22, 1, 0, 2}, /* TxD5 */ 71 {5, 21, 1, 0, 2}, /* TxD6 */ 72 {5, 20, 1, 0, 2}, /* TxD7 */ 73 {5, 15, 2, 0, 2}, /* RxD0 */ 74 {5, 14, 2, 0, 2}, /* RxD1 */ 75 {5, 13, 2, 0, 2}, /* RxD2 */ 76 {5, 12, 2, 0, 2}, /* RxD3 */ 77 {5, 29, 2, 0, 2}, /* RxD4 */ 78 {5, 28, 2, 0, 2}, /* RxD5 */ 79 {5, 27, 2, 0, 3}, /* RxD6 */ 80 {5, 26, 2, 0, 2}, /* RxD7 */ 81 {5, 11, 1, 0, 2}, /* TX_EN */ 82 {5, 24, 1, 0, 2}, /* TX_ER */ 83 {5, 16, 2, 0, 2}, /* RX_DV */ 84 {5, 30, 2, 0, 2}, /* RX_ER */ 85 {5, 17, 2, 0, 2}, /* RX_CLK */ 86 {5, 19, 1, 0, 2}, /* GTX_CLK */ 87 {1, 31, 2, 0, 3}, /* GTX125 */ 88 {4, 6, 3, 0, 2}, /* MDIO */ 89 {4, 5, 1, 0, 2}, /* MDC */ 90 {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ 91 }; 92 93 94 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 95 extern void ddr_enable_ecc(unsigned int dram_size); 96 #endif 97 98 extern long int spd_sdram(void); 99 100 void local_bus_init(void); 101 void sdram_init(void); 102 103 int board_early_init_f (void) 104 { 105 /* 106 * Initialize local bus. 107 */ 108 local_bus_init (); 109 110 enable_8568mds_duart(); 111 enable_8568mds_flash_write(); 112 #if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2) 113 reset_8568mds_uccs(); 114 #endif 115 #if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS) 116 enable_8568mds_qe_mdio(); 117 #endif 118 119 #ifdef CFG_I2C2_OFFSET 120 /* Enable I2C2_SCL and I2C2_SDA */ 121 volatile struct par_io *port_c; 122 port_c = (struct par_io*)(CFG_IMMR + 0xe0140); 123 port_c->cpdir2 |= 0x0f000000; 124 port_c->cppar2 &= ~0x0f000000; 125 port_c->cppar2 |= 0x0a000000; 126 #endif 127 128 return 0; 129 } 130 131 int checkboard (void) 132 { 133 printf ("Board: 8568 MDS\n"); 134 135 return 0; 136 } 137 138 long int 139 initdram(int board_type) 140 { 141 long dram_size = 0; 142 143 puts("Initializing\n"); 144 145 #if defined(CONFIG_DDR_DLL) 146 { 147 /* 148 * Work around to stabilize DDR DLL MSYNC_IN. 149 * Errata DDR9 seems to have been fixed. 150 * This is now the workaround for Errata DDR11: 151 * Override DLL = 1, Course Adj = 1, Tap Select = 0 152 */ 153 154 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 155 156 gur->ddrdllcr = 0x81000000; 157 asm("sync;isync;msync"); 158 udelay(200); 159 } 160 #endif 161 dram_size = spd_sdram(); 162 163 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 164 /* 165 * Initialize and enable DDR ECC. 166 */ 167 ddr_enable_ecc(dram_size); 168 #endif 169 /* 170 * SDRAM Initialization 171 */ 172 sdram_init(); 173 174 puts(" DDR: "); 175 return dram_size; 176 } 177 178 /* 179 * Initialize Local Bus 180 */ 181 void 182 local_bus_init(void) 183 { 184 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 185 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); 186 187 uint clkdiv; 188 uint lbc_hz; 189 sys_info_t sysinfo; 190 191 get_sys_info(&sysinfo); 192 clkdiv = (lbc->lcrr & 0x0f) * 2; 193 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; 194 195 gur->lbiuiplldcr1 = 0x00078080; 196 if (clkdiv == 16) { 197 gur->lbiuiplldcr0 = 0x7c0f1bf0; 198 } else if (clkdiv == 8) { 199 gur->lbiuiplldcr0 = 0x6c0f1bf0; 200 } else if (clkdiv == 4) { 201 gur->lbiuiplldcr0 = 0x5c0f1bf0; 202 } 203 204 lbc->lcrr |= 0x00030000; 205 206 asm("sync;isync;msync"); 207 } 208 209 /* 210 * Initialize SDRAM memory on the Local Bus. 211 */ 212 void 213 sdram_init(void) 214 { 215 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) 216 217 uint idx; 218 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); 219 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; 220 uint lsdmr_common; 221 222 puts(" SDRAM: "); 223 224 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); 225 226 /* 227 * Setup SDRAM Base and Option Registers 228 */ 229 lbc->or2 = CFG_OR2_PRELIM; 230 asm("msync"); 231 232 lbc->br2 = CFG_BR2_PRELIM; 233 asm("msync"); 234 235 lbc->lbcr = CFG_LBC_LBCR; 236 asm("msync"); 237 238 239 lbc->lsrt = CFG_LBC_LSRT; 240 lbc->mrtpr = CFG_LBC_MRTPR; 241 asm("msync"); 242 243 /* 244 * MPC8568 uses "new" 15-16 style addressing. 245 */ 246 lsdmr_common = CFG_LBC_LSDMR_COMMON; 247 lsdmr_common |= CFG_LBC_LSDMR_BSMA1516; 248 249 /* 250 * Issue PRECHARGE ALL command. 251 */ 252 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL; 253 asm("sync;msync"); 254 *sdram_addr = 0xff; 255 ppcDcbf((unsigned long) sdram_addr); 256 udelay(100); 257 258 /* 259 * Issue 8 AUTO REFRESH commands. 260 */ 261 for (idx = 0; idx < 8; idx++) { 262 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH; 263 asm("sync;msync"); 264 *sdram_addr = 0xff; 265 ppcDcbf((unsigned long) sdram_addr); 266 udelay(100); 267 } 268 269 /* 270 * Issue 8 MODE-set command. 271 */ 272 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW; 273 asm("sync;msync"); 274 *sdram_addr = 0xff; 275 ppcDcbf((unsigned long) sdram_addr); 276 udelay(100); 277 278 /* 279 * Issue NORMAL OP command. 280 */ 281 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL; 282 asm("sync;msync"); 283 *sdram_addr = 0xff; 284 ppcDcbf((unsigned long) sdram_addr); 285 udelay(200); /* Overkill. Must wait > 200 bus cycles */ 286 287 #endif /* enable SDRAM init */ 288 } 289 290 #if defined(CFG_DRAM_TEST) 291 int 292 testdram(void) 293 { 294 uint *pstart = (uint *) CFG_MEMTEST_START; 295 uint *pend = (uint *) CFG_MEMTEST_END; 296 uint *p; 297 298 printf("Testing DRAM from 0x%08x to 0x%08x\n", 299 CFG_MEMTEST_START, 300 CFG_MEMTEST_END); 301 302 printf("DRAM test phase 1:\n"); 303 for (p = pstart; p < pend; p++) 304 *p = 0xaaaaaaaa; 305 306 for (p = pstart; p < pend; p++) { 307 if (*p != 0xaaaaaaaa) { 308 printf ("DRAM test fails at: %08x\n", (uint) p); 309 return 1; 310 } 311 } 312 313 printf("DRAM test phase 2:\n"); 314 for (p = pstart; p < pend; p++) 315 *p = 0x55555555; 316 317 for (p = pstart; p < pend; p++) { 318 if (*p != 0x55555555) { 319 printf ("DRAM test fails at: %08x\n", (uint) p); 320 return 1; 321 } 322 } 323 324 printf("DRAM test passed.\n"); 325 return 0; 326 } 327 #endif 328 329 #if defined(CONFIG_PCI) 330 #ifndef CONFIG_PCI_PNP 331 static struct pci_config_table pci_mpc8568mds_config_table[] = { 332 { 333 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 334 pci_cfgfunc_config_device, 335 {PCI_ENET0_IOADDR, 336 PCI_ENET0_MEMADDR, 337 PCI_COMMON_MEMORY | PCI_COMMAND_MASTER} 338 }, 339 {} 340 }; 341 #endif 342 343 static struct pci_controller pci1_hose = { 344 #ifndef CONFIG_PCI_PNP 345 config_table: pci_mpc8568mds_config_table, 346 #endif 347 }; 348 #endif /* CONFIG_PCI */ 349 350 #ifdef CONFIG_PCIE1 351 static struct pci_controller pcie1_hose; 352 #endif /* CONFIG_PCIE1 */ 353 354 int first_free_busno = 0; 355 356 /* 357 * pib_init() -- Initialize the PCA9555 IO expander on the PIB board 358 */ 359 void 360 pib_init(void) 361 { 362 u8 val8, orig_i2c_bus; 363 /* 364 * Assign PIB PMC2/3 to PCI bus 365 */ 366 367 /*switch temporarily to I2C bus #2 */ 368 orig_i2c_bus = i2c_get_bus_num(); 369 i2c_set_bus_num(1); 370 371 val8 = 0x00; 372 i2c_write(0x23, 0x6, 1, &val8, 1); 373 i2c_write(0x23, 0x7, 1, &val8, 1); 374 val8 = 0xff; 375 i2c_write(0x23, 0x2, 1, &val8, 1); 376 i2c_write(0x23, 0x3, 1, &val8, 1); 377 378 val8 = 0x00; 379 i2c_write(0x26, 0x6, 1, &val8, 1); 380 val8 = 0x34; 381 i2c_write(0x26, 0x7, 1, &val8, 1); 382 val8 = 0xf9; 383 i2c_write(0x26, 0x2, 1, &val8, 1); 384 val8 = 0xff; 385 i2c_write(0x26, 0x3, 1, &val8, 1); 386 387 val8 = 0x00; 388 i2c_write(0x27, 0x6, 1, &val8, 1); 389 i2c_write(0x27, 0x7, 1, &val8, 1); 390 val8 = 0xff; 391 i2c_write(0x27, 0x2, 1, &val8, 1); 392 val8 = 0xef; 393 i2c_write(0x27, 0x3, 1, &val8, 1); 394 395 asm("eieio"); 396 } 397 398 #ifdef CONFIG_PCI 399 void 400 pci_init_board(void) 401 { 402 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 403 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 404 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; 405 406 #ifdef CONFIG_PCI1 407 { 408 pib_init(); 409 410 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; 411 extern void fsl_pci_init(struct pci_controller *hose); 412 struct pci_controller *hose = &pci1_hose; 413 414 uint pci_32 = 1; /* PORDEVSR[15] */ 415 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ 416 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ 417 418 uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6); 419 420 uint pci_speed = 66666000; 421 422 if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { 423 printf (" PCI: %d bit, %s MHz, %s, %s, %s\n", 424 (pci_32) ? 32 : 64, 425 (pci_speed == 33333000) ? "33" : 426 (pci_speed == 66666000) ? "66" : "unknown", 427 pci_clk_sel ? "sync" : "async", 428 pci_agent ? "agent" : "host", 429 pci_arb ? "arbiter" : "external-arbiter" 430 ); 431 432 /* inbound */ 433 pci_set_region(hose->regions + 0, 434 CFG_PCI_MEMORY_BUS, 435 CFG_PCI_MEMORY_PHYS, 436 CFG_PCI_MEMORY_SIZE, 437 PCI_REGION_MEM | PCI_REGION_MEMORY); 438 439 /* outbound memory */ 440 pci_set_region(hose->regions + 1, 441 CFG_PCI1_MEM_BASE, 442 CFG_PCI1_MEM_PHYS, 443 CFG_PCI1_MEM_SIZE, 444 PCI_REGION_MEM); 445 446 /* outbound io */ 447 pci_set_region(hose->regions + 2, 448 CFG_PCI1_IO_BASE, 449 CFG_PCI1_IO_PHYS, 450 CFG_PCI1_IO_SIZE, 451 PCI_REGION_IO); 452 453 hose->region_count = 3; 454 455 hose->first_busno = first_free_busno; 456 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 457 458 fsl_pci_init(hose); 459 first_free_busno = hose->last_busno+1; 460 printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); 461 } else { 462 printf (" PCI: disabled\n"); 463 } 464 } 465 #else 466 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ 467 #endif 468 469 #ifdef CONFIG_PCIE1 470 { 471 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; 472 extern void fsl_pci_init(struct pci_controller *hose); 473 struct pci_controller *hose = &pcie1_hose; 474 int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); 475 476 int pcie_configured = io_sel >= 1; 477 478 if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ 479 printf ("\n PCIE connected to slot as %s (base address %x)", 480 pcie_ep ? "End Point" : "Root Complex", 481 (uint)pci); 482 483 if (pci->pme_msg_det) { 484 pci->pme_msg_det = 0xffffffff; 485 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 486 } 487 printf ("\n"); 488 489 /* inbound */ 490 pci_set_region(hose->regions + 0, 491 CFG_PCI_MEMORY_BUS, 492 CFG_PCI_MEMORY_PHYS, 493 CFG_PCI_MEMORY_SIZE, 494 PCI_REGION_MEM | PCI_REGION_MEMORY); 495 496 /* outbound memory */ 497 pci_set_region(hose->regions + 1, 498 CFG_PCIE1_MEM_BASE, 499 CFG_PCIE1_MEM_PHYS, 500 CFG_PCIE1_MEM_SIZE, 501 PCI_REGION_MEM); 502 503 /* outbound io */ 504 pci_set_region(hose->regions + 2, 505 CFG_PCIE1_IO_BASE, 506 CFG_PCIE1_IO_PHYS, 507 CFG_PCIE1_IO_SIZE, 508 PCI_REGION_IO); 509 510 hose->region_count = 3; 511 512 hose->first_busno=first_free_busno; 513 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 514 515 fsl_pci_init(hose); 516 printf ("PCIE on bus %02x - %02x\n",hose->first_busno,hose->last_busno); 517 518 first_free_busno=hose->last_busno+1; 519 520 } else { 521 printf (" PCIE: disabled\n"); 522 } 523 } 524 #else 525 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 526 #endif 527 } 528 #endif /* CONFIG_PCI */ 529 530 #if defined(CONFIG_OF_BOARD_SETUP) 531 void 532 ft_board_setup(void *blob, bd_t *bd) 533 { 534 int node, tmp[2]; 535 const char *path; 536 537 ft_cpu_setup(blob, bd); 538 539 node = fdt_path_offset(blob, "/aliases"); 540 tmp[0] = 0; 541 if (node >= 0) { 542 #ifdef CONFIG_PCI1 543 path = fdt_getprop(blob, node, "pci0", NULL); 544 if (path) { 545 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; 546 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 547 } 548 #endif 549 #ifdef CONFIG_PCIE1 550 path = fdt_getprop(blob, node, "pci1", NULL); 551 if (path) { 552 tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; 553 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 554 } 555 #endif 556 } 557 } 558 #endif 559