1 /* 2 * Copyright 2004, 2007, 2009-2010 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <pci.h> 27 #include <asm/processor.h> 28 #include <asm/mmu.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/fsl_serdes.h> 33 #include <spd_sdram.h> 34 #include <miiphy.h> 35 #include <libfdt.h> 36 #include <fdt_support.h> 37 38 #include "../common/cadmus.h" 39 #include "../common/eeprom.h" 40 #include "../common/via.h" 41 42 DECLARE_GLOBAL_DATA_PTR; 43 44 void local_bus_init(void); 45 void sdram_init(void); 46 47 int checkboard (void) 48 { 49 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 50 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 51 52 /* PCI slot in USER bits CSR[6:7] by convention. */ 53 uint pci_slot = get_pci_slot (); 54 55 uint cpu_board_rev = get_cpu_board_revision (); 56 57 printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", 58 get_board_version (), pci_slot); 59 60 printf ("CPU Board Revision %d.%d (0x%04x)\n", 61 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), 62 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); 63 /* 64 * Initialize local bus. 65 */ 66 local_bus_init (); 67 68 /* 69 * Hack TSEC 3 and 4 IO voltages. 70 */ 71 gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ 72 73 ecm->eedr = 0xffffffff; /* clear ecm errors */ 74 ecm->eeer = 0xffffffff; /* enable ecm errors */ 75 return 0; 76 } 77 78 phys_size_t 79 initdram(int board_type) 80 { 81 long dram_size = 0; 82 83 puts("Initializing\n"); 84 85 #if defined(CONFIG_DDR_DLL) 86 { 87 /* 88 * Work around to stabilize DDR DLL MSYNC_IN. 89 * Errata DDR9 seems to have been fixed. 90 * This is now the workaround for Errata DDR11: 91 * Override DLL = 1, Course Adj = 1, Tap Select = 0 92 */ 93 94 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 95 96 gur->ddrdllcr = 0x81000000; 97 asm("sync;isync;msync"); 98 udelay(200); 99 } 100 #endif 101 102 dram_size = fsl_ddr_sdram(); 103 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 104 dram_size *= 0x100000; 105 106 /* 107 * SDRAM Initialization 108 */ 109 sdram_init(); 110 111 puts(" DDR: "); 112 return dram_size; 113 } 114 115 /* 116 * Initialize Local Bus 117 */ 118 void 119 local_bus_init(void) 120 { 121 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 122 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 123 124 uint clkdiv; 125 uint lbc_hz; 126 sys_info_t sysinfo; 127 128 get_sys_info(&sysinfo); 129 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; 130 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; 131 132 gur->lbiuiplldcr1 = 0x00078080; 133 if (clkdiv == 16) { 134 gur->lbiuiplldcr0 = 0x7c0f1bf0; 135 } else if (clkdiv == 8) { 136 gur->lbiuiplldcr0 = 0x6c0f1bf0; 137 } else if (clkdiv == 4) { 138 gur->lbiuiplldcr0 = 0x5c0f1bf0; 139 } 140 141 lbc->lcrr |= 0x00030000; 142 143 asm("sync;isync;msync"); 144 145 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ 146 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ 147 } 148 149 /* 150 * Initialize SDRAM memory on the Local Bus. 151 */ 152 void 153 sdram_init(void) 154 { 155 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) 156 157 uint idx; 158 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 159 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; 160 uint cpu_board_rev; 161 uint lsdmr_common; 162 163 puts(" SDRAM: "); 164 165 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); 166 167 /* 168 * Setup SDRAM Base and Option Registers 169 */ 170 set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); 171 set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); 172 lbc->lbcr = CONFIG_SYS_LBC_LBCR; 173 asm("msync"); 174 175 lbc->lsrt = CONFIG_SYS_LBC_LSRT; 176 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; 177 asm("msync"); 178 179 /* 180 * MPC8548 uses "new" 15-16 style addressing. 181 */ 182 cpu_board_rev = get_cpu_board_revision(); 183 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; 184 lsdmr_common |= LSDMR_BSMA1516; 185 186 /* 187 * Issue PRECHARGE ALL command. 188 */ 189 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; 190 asm("sync;msync"); 191 *sdram_addr = 0xff; 192 ppcDcbf((unsigned long) sdram_addr); 193 udelay(100); 194 195 /* 196 * Issue 8 AUTO REFRESH commands. 197 */ 198 for (idx = 0; idx < 8; idx++) { 199 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; 200 asm("sync;msync"); 201 *sdram_addr = 0xff; 202 ppcDcbf((unsigned long) sdram_addr); 203 udelay(100); 204 } 205 206 /* 207 * Issue 8 MODE-set command. 208 */ 209 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; 210 asm("sync;msync"); 211 *sdram_addr = 0xff; 212 ppcDcbf((unsigned long) sdram_addr); 213 udelay(100); 214 215 /* 216 * Issue NORMAL OP command. 217 */ 218 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; 219 asm("sync;msync"); 220 *sdram_addr = 0xff; 221 ppcDcbf((unsigned long) sdram_addr); 222 udelay(200); /* Overkill. Must wait > 200 bus cycles */ 223 224 #endif /* enable SDRAM init */ 225 } 226 227 #if defined(CONFIG_PCI) || defined(CONFIG_PCI1) 228 /* For some reason the Tundra PCI bridge shows up on itself as a 229 * different device. Work around that by refusing to configure it. 230 */ 231 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } 232 233 static struct pci_config_table pci_mpc85xxcds_config_table[] = { 234 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, 235 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, 236 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, 237 mpc85xx_config_via_usbide, {0,0,0}}, 238 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, 239 mpc85xx_config_via_usb, {0,0,0}}, 240 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, 241 mpc85xx_config_via_usb2, {0,0,0}}, 242 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, 243 mpc85xx_config_via_power, {0,0,0}}, 244 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, 245 mpc85xx_config_via_ac97, {0,0,0}}, 246 {}, 247 }; 248 249 static struct pci_controller pci1_hose = { 250 config_table: pci_mpc85xxcds_config_table}; 251 #endif /* CONFIG_PCI */ 252 253 #ifdef CONFIG_PCI2 254 static struct pci_controller pci2_hose; 255 #endif /* CONFIG_PCI2 */ 256 257 #ifdef CONFIG_PCIE1 258 static struct pci_controller pcie1_hose; 259 #endif /* CONFIG_PCIE1 */ 260 261 void pci_init_board(void) 262 { 263 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 264 struct fsl_pci_info pci_info[4]; 265 u32 devdisr, pordevsr, io_sel; 266 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; 267 int first_free_busno = 0; 268 int num = 0; 269 270 int pcie_ep, pcie_configured; 271 272 devdisr = in_be32(&gur->devdisr); 273 pordevsr = in_be32(&gur->pordevsr); 274 porpllsr = in_be32(&gur->porpllsr); 275 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 276 277 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); 278 279 #ifdef CONFIG_PCI1 280 pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ 281 pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ 282 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; 283 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; 284 285 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 286 SET_STD_PCI_INFO(pci_info[num], 1); 287 pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); 288 printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", 289 (pci_32) ? 32 : 64, 290 (pci_speed == 33333000) ? "33" : 291 (pci_speed == 66666000) ? "66" : "unknown", 292 pci_clk_sel ? "sync" : "async", 293 pci_agent ? "agent" : "host", 294 pci_arb ? "arbiter" : "external-arbiter", 295 pci_info[num].regs); 296 297 first_free_busno = fsl_pci_init_port(&pci_info[num++], 298 &pci1_hose, first_free_busno); 299 300 #ifdef CONFIG_PCIX_CHECK 301 if (!(pordevsr & MPC85xx_PORDEVSR_PCI1)) { 302 /* PCI-X init */ 303 if (CONFIG_SYS_CLK_FREQ < 66000000) 304 printf("PCI-X will only work at 66 MHz\n"); 305 306 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ 307 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; 308 pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16); 309 } 310 #endif 311 } else { 312 printf("PCI: disabled\n"); 313 } 314 315 puts("\n"); 316 #else 317 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ 318 #endif 319 320 #ifdef CONFIG_PCI2 321 { 322 uint pci2_clk_sel = porpllsr & 0x4000; /* PORPLLSR[17] */ 323 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ 324 if (pci_dual) { 325 printf("PCI2: 32 bit, 66 MHz, %s\n", 326 pci2_clk_sel ? "sync" : "async"); 327 } else { 328 printf("PCI2: disabled\n"); 329 } 330 } 331 #else 332 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */ 333 #endif /* CONFIG_PCI2 */ 334 335 #ifdef CONFIG_PCIE1 336 pcie_configured = is_serdes_configured(PCIE1); 337 338 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 339 SET_STD_PCIE_INFO(pci_info[num], 1); 340 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); 341 printf("PCIE1: connected to Slot as %s (base addr %lx)\n", 342 pcie_ep ? "Endpoint" : "Root Complex", 343 pci_info[num].regs); 344 345 first_free_busno = fsl_pci_init_port(&pci_info[num++], 346 &pcie1_hose, first_free_busno); 347 } else { 348 printf("PCIE1: disabled\n"); 349 } 350 351 puts("\n"); 352 #else 353 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ 354 #endif 355 } 356 357 int last_stage_init(void) 358 { 359 unsigned short temp; 360 361 /* Change the resistors for the PHY */ 362 /* This is needed to get the RGMII working for the 1.3+ 363 * CDS cards */ 364 if (get_board_version() == 0x13) { 365 miiphy_write(CONFIG_TSEC1_NAME, 366 TSEC1_PHY_ADDR, 29, 18); 367 368 miiphy_read(CONFIG_TSEC1_NAME, 369 TSEC1_PHY_ADDR, 30, &temp); 370 371 temp = (temp & 0xf03f); 372 temp |= 2 << 9; /* 36 ohm */ 373 temp |= 2 << 6; /* 39 ohm */ 374 375 miiphy_write(CONFIG_TSEC1_NAME, 376 TSEC1_PHY_ADDR, 30, temp); 377 378 miiphy_write(CONFIG_TSEC1_NAME, 379 TSEC1_PHY_ADDR, 29, 3); 380 381 miiphy_write(CONFIG_TSEC1_NAME, 382 TSEC1_PHY_ADDR, 30, 0x8000); 383 } 384 385 return 0; 386 } 387 388 389 #if defined(CONFIG_OF_BOARD_SETUP) 390 void ft_pci_setup(void *blob, bd_t *bd) 391 { 392 FT_FSL_PCI_SETUP; 393 } 394 #endif 395