1 /* 2 * Copyright 2007 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/immap_85xx.h> 28 #include <asm/immap_fsl_pci.h> 29 #include <asm/io.h> 30 #include <spd.h> 31 #include <miiphy.h> 32 #include <libfdt.h> 33 #include <fdt_support.h> 34 35 #include "../common/pixis.h" 36 37 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 38 extern void ddr_enable_ecc(unsigned int dram_size); 39 #endif 40 41 extern long int spd_sdram(void); 42 43 void sdram_init(void); 44 45 int board_early_init_f (void) 46 { 47 return 0; 48 } 49 50 int checkboard (void) 51 { 52 volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; 53 volatile ccsr_gur_t *gur = &immap->im_gur; 54 volatile ccsr_lbc_t *lbc = &immap->im_lbc; 55 volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm; 56 57 if ((uint)&gur->porpllsr != 0xe00e0000) { 58 printf("immap size error %x\n",&gur->porpllsr); 59 } 60 printf ("Board: MPC8544DS\n"); 61 62 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ 63 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ 64 ecm->eedr = 0xffffffff; /* Clear ecm errors */ 65 ecm->eeer = 0xffffffff; /* Enable ecm errors */ 66 67 return 0; 68 } 69 70 long int 71 initdram(int board_type) 72 { 73 long dram_size = 0; 74 75 puts("Initializing\n"); 76 77 dram_size = spd_sdram(); 78 79 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 80 /* 81 * Initialize and enable DDR ECC. 82 */ 83 ddr_enable_ecc(dram_size); 84 #endif 85 puts(" DDR: "); 86 return dram_size; 87 } 88 89 #if defined(CFG_DRAM_TEST) 90 int 91 testdram(void) 92 { 93 uint *pstart = (uint *) CFG_MEMTEST_START; 94 uint *pend = (uint *) CFG_MEMTEST_END; 95 uint *p; 96 97 printf("Testing DRAM from 0x%08x to 0x%08x\n", 98 CFG_MEMTEST_START, 99 CFG_MEMTEST_END); 100 101 printf("DRAM test phase 1:\n"); 102 for (p = pstart; p < pend; p++) 103 *p = 0xaaaaaaaa; 104 105 for (p = pstart; p < pend; p++) { 106 if (*p != 0xaaaaaaaa) { 107 printf ("DRAM test fails at: %08x\n", (uint) p); 108 return 1; 109 } 110 } 111 112 printf("DRAM test phase 2:\n"); 113 for (p = pstart; p < pend; p++) 114 *p = 0x55555555; 115 116 for (p = pstart; p < pend; p++) { 117 if (*p != 0x55555555) { 118 printf ("DRAM test fails at: %08x\n", (uint) p); 119 return 1; 120 } 121 } 122 123 printf("DRAM test passed.\n"); 124 return 0; 125 } 126 #endif 127 128 #ifdef CONFIG_PCI1 129 static struct pci_controller pci1_hose; 130 #endif 131 132 #ifdef CONFIG_PCIE1 133 static struct pci_controller pcie1_hose; 134 #endif 135 136 #ifdef CONFIG_PCIE2 137 static struct pci_controller pcie2_hose; 138 #endif 139 140 #ifdef CONFIG_PCIE3 141 static struct pci_controller pcie3_hose; 142 #endif 143 144 int first_free_busno=0; 145 146 void 147 pci_init_board(void) 148 { 149 volatile immap_t *immap = (immap_t *)CFG_IMMR; 150 volatile ccsr_gur_t *gur = &immap->im_gur; 151 uint devdisr = gur->devdisr; 152 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 153 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; 154 155 debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", 156 devdisr, io_sel, host_agent); 157 158 if (io_sel & 1) { 159 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) 160 printf (" eTSEC1 is in sgmii mode.\n"); 161 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) 162 printf (" eTSEC3 is in sgmii mode.\n"); 163 } 164 165 #ifdef CONFIG_PCIE3 166 { 167 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR; 168 extern void fsl_pci_init(struct pci_controller *hose); 169 struct pci_controller *hose = &pcie3_hose; 170 int pcie_ep = (host_agent == 3); 171 int pcie_configured = io_sel >= 1; 172 173 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 174 printf ("\n PCIE3 connected to ULI as %s (base address %x)", 175 pcie_ep ? "End Point" : "Root Complex", 176 (uint)pci); 177 if (pci->pme_msg_det) { 178 pci->pme_msg_det = 0xffffffff; 179 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 180 } 181 printf ("\n"); 182 183 /* inbound */ 184 pci_set_region(hose->regions + 0, 185 CFG_PCI_MEMORY_BUS, 186 CFG_PCI_MEMORY_PHYS, 187 CFG_PCI_MEMORY_SIZE, 188 PCI_REGION_MEM | PCI_REGION_MEMORY); 189 190 /* outbound memory */ 191 pci_set_region(hose->regions + 1, 192 CFG_PCIE3_MEM_BASE, 193 CFG_PCIE3_MEM_PHYS, 194 CFG_PCIE3_MEM_SIZE, 195 PCI_REGION_MEM); 196 197 /* outbound io */ 198 pci_set_region(hose->regions + 2, 199 CFG_PCIE3_IO_BASE, 200 CFG_PCIE3_IO_PHYS, 201 CFG_PCIE3_IO_SIZE, 202 PCI_REGION_IO); 203 204 hose->region_count = 3; 205 #ifdef CFG_PCIE3_MEM_BASE2 206 /* outbound memory */ 207 pci_set_region(hose->regions + 3, 208 CFG_PCIE3_MEM_BASE2, 209 CFG_PCIE3_MEM_PHYS2, 210 CFG_PCIE3_MEM_SIZE2, 211 PCI_REGION_MEM); 212 hose->region_count++; 213 #endif 214 hose->first_busno=first_free_busno; 215 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 216 217 fsl_pci_init(hose); 218 219 first_free_busno=hose->last_busno+1; 220 printf (" PCIE3 on bus %02x - %02x\n", 221 hose->first_busno,hose->last_busno); 222 223 /* 224 * Activate ULI1575 legacy chip by performing a fake 225 * memory access. Needed to make ULI RTC work. 226 */ 227 in_be32((u32 *)CFG_PCIE3_MEM_BASE); 228 } else { 229 printf (" PCIE3: disabled\n"); 230 } 231 232 } 233 #else 234 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ 235 #endif 236 237 #ifdef CONFIG_PCIE1 238 { 239 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; 240 extern void fsl_pci_init(struct pci_controller *hose); 241 struct pci_controller *hose = &pcie1_hose; 242 int pcie_ep = (host_agent == 5); 243 int pcie_configured = io_sel & 6; 244 245 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 246 printf ("\n PCIE1 connected to Slot2 as %s (base address %x)", 247 pcie_ep ? "End Point" : "Root Complex", 248 (uint)pci); 249 if (pci->pme_msg_det) { 250 pci->pme_msg_det = 0xffffffff; 251 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 252 } 253 printf ("\n"); 254 255 /* inbound */ 256 pci_set_region(hose->regions + 0, 257 CFG_PCI_MEMORY_BUS, 258 CFG_PCI_MEMORY_PHYS, 259 CFG_PCI_MEMORY_SIZE, 260 PCI_REGION_MEM | PCI_REGION_MEMORY); 261 262 /* outbound memory */ 263 pci_set_region(hose->regions + 1, 264 CFG_PCIE1_MEM_BASE, 265 CFG_PCIE1_MEM_PHYS, 266 CFG_PCIE1_MEM_SIZE, 267 PCI_REGION_MEM); 268 269 /* outbound io */ 270 pci_set_region(hose->regions + 2, 271 CFG_PCIE1_IO_BASE, 272 CFG_PCIE1_IO_PHYS, 273 CFG_PCIE1_IO_SIZE, 274 PCI_REGION_IO); 275 276 hose->region_count = 3; 277 #ifdef CFG_PCIE1_MEM_BASE2 278 /* outbound memory */ 279 pci_set_region(hose->regions + 3, 280 CFG_PCIE1_MEM_BASE2, 281 CFG_PCIE1_MEM_PHYS2, 282 CFG_PCIE1_MEM_SIZE2, 283 PCI_REGION_MEM); 284 hose->region_count++; 285 #endif 286 hose->first_busno=first_free_busno; 287 288 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 289 290 fsl_pci_init(hose); 291 292 first_free_busno=hose->last_busno+1; 293 printf(" PCIE1 on bus %02x - %02x\n", 294 hose->first_busno,hose->last_busno); 295 296 } else { 297 printf (" PCIE1: disabled\n"); 298 } 299 300 } 301 #else 302 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 303 #endif 304 305 #ifdef CONFIG_PCIE2 306 { 307 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR; 308 extern void fsl_pci_init(struct pci_controller *hose); 309 struct pci_controller *hose = &pcie2_hose; 310 int pcie_ep = (host_agent == 3); 311 int pcie_configured = io_sel & 4; 312 313 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 314 printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)", 315 pcie_ep ? "End Point" : "Root Complex", 316 (uint)pci); 317 if (pci->pme_msg_det) { 318 pci->pme_msg_det = 0xffffffff; 319 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 320 } 321 printf ("\n"); 322 323 /* inbound */ 324 pci_set_region(hose->regions + 0, 325 CFG_PCI_MEMORY_BUS, 326 CFG_PCI_MEMORY_PHYS, 327 CFG_PCI_MEMORY_SIZE, 328 PCI_REGION_MEM | PCI_REGION_MEMORY); 329 330 /* outbound memory */ 331 pci_set_region(hose->regions + 1, 332 CFG_PCIE2_MEM_BASE, 333 CFG_PCIE2_MEM_PHYS, 334 CFG_PCIE2_MEM_SIZE, 335 PCI_REGION_MEM); 336 337 /* outbound io */ 338 pci_set_region(hose->regions + 2, 339 CFG_PCIE2_IO_BASE, 340 CFG_PCIE2_IO_PHYS, 341 CFG_PCIE2_IO_SIZE, 342 PCI_REGION_IO); 343 344 hose->region_count = 3; 345 #ifdef CFG_PCIE2_MEM_BASE2 346 /* outbound memory */ 347 pci_set_region(hose->regions + 3, 348 CFG_PCIE2_MEM_BASE2, 349 CFG_PCIE2_MEM_PHYS2, 350 CFG_PCIE2_MEM_SIZE2, 351 PCI_REGION_MEM); 352 hose->region_count++; 353 #endif 354 hose->first_busno=first_free_busno; 355 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 356 357 fsl_pci_init(hose); 358 first_free_busno=hose->last_busno+1; 359 printf (" PCIE2 on bus %02x - %02x\n", 360 hose->first_busno,hose->last_busno); 361 362 } else { 363 printf (" PCIE2: disabled\n"); 364 } 365 366 } 367 #else 368 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ 369 #endif 370 371 372 #ifdef CONFIG_PCI1 373 { 374 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; 375 extern void fsl_pci_init(struct pci_controller *hose); 376 struct pci_controller *hose = &pci1_hose; 377 378 uint pci_agent = (host_agent == 6); 379 uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ 380 uint pci_32 = 1; 381 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ 382 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ 383 384 385 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 386 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n", 387 (pci_32) ? 32 : 64, 388 (pci_speed == 33333000) ? "33" : 389 (pci_speed == 66666000) ? "66" : "unknown", 390 pci_clk_sel ? "sync" : "async", 391 pci_agent ? "agent" : "host", 392 pci_arb ? "arbiter" : "external-arbiter", 393 (uint)pci 394 ); 395 396 /* inbound */ 397 pci_set_region(hose->regions + 0, 398 CFG_PCI_MEMORY_BUS, 399 CFG_PCI_MEMORY_PHYS, 400 CFG_PCI_MEMORY_SIZE, 401 PCI_REGION_MEM | PCI_REGION_MEMORY); 402 403 /* outbound memory */ 404 pci_set_region(hose->regions + 1, 405 CFG_PCI1_MEM_BASE, 406 CFG_PCI1_MEM_PHYS, 407 CFG_PCI1_MEM_SIZE, 408 PCI_REGION_MEM); 409 410 /* outbound io */ 411 pci_set_region(hose->regions + 2, 412 CFG_PCI1_IO_BASE, 413 CFG_PCI1_IO_PHYS, 414 CFG_PCI1_IO_SIZE, 415 PCI_REGION_IO); 416 hose->region_count = 3; 417 #ifdef CFG_PCIE3_MEM_BASE2 418 /* outbound memory */ 419 pci_set_region(hose->regions + 3, 420 CFG_PCIE3_MEM_BASE2, 421 CFG_PCIE3_MEM_PHYS2, 422 CFG_PCIE3_MEM_SIZE2, 423 PCI_REGION_MEM); 424 hose->region_count++; 425 #endif 426 hose->first_busno=first_free_busno; 427 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 428 429 fsl_pci_init(hose); 430 first_free_busno=hose->last_busno+1; 431 printf ("PCI on bus %02x - %02x\n", 432 hose->first_busno,hose->last_busno); 433 } else { 434 printf (" PCI: disabled\n"); 435 } 436 } 437 #else 438 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ 439 #endif 440 } 441 442 443 int last_stage_init(void) 444 { 445 return 0; 446 } 447 448 449 unsigned long 450 get_board_sys_clk(ulong dummy) 451 { 452 u8 i, go_bit, rd_clks; 453 ulong val = 0; 454 455 go_bit = in8(PIXIS_BASE + PIXIS_VCTL); 456 go_bit &= 0x01; 457 458 rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0); 459 rd_clks &= 0x1C; 460 461 /* 462 * Only if both go bit and the SCLK bit in VCFGEN0 are set 463 * should we be using the AUX register. Remember, we also set the 464 * GO bit to boot from the alternate bank on the on-board flash 465 */ 466 467 if (go_bit) { 468 if (rd_clks == 0x1c) 469 i = in8(PIXIS_BASE + PIXIS_AUX); 470 else 471 i = in8(PIXIS_BASE + PIXIS_SPD); 472 } else { 473 i = in8(PIXIS_BASE + PIXIS_SPD); 474 } 475 476 i &= 0x07; 477 478 switch (i) { 479 case 0: 480 val = 33333333; 481 break; 482 case 1: 483 val = 40000000; 484 break; 485 case 2: 486 val = 50000000; 487 break; 488 case 3: 489 val = 66666666; 490 break; 491 case 4: 492 val = 83000000; 493 break; 494 case 5: 495 val = 100000000; 496 break; 497 case 6: 498 val = 133333333; 499 break; 500 case 7: 501 val = 166666666; 502 break; 503 } 504 505 return val; 506 } 507 508 #if defined(CONFIG_OF_BOARD_SETUP) 509 510 void 511 ft_board_setup(void *blob, bd_t *bd) 512 { 513 int node, tmp[2]; 514 const char *path; 515 516 ft_cpu_setup(blob, bd); 517 518 node = fdt_path_offset(blob, "/aliases"); 519 tmp[0] = 0; 520 if (node >= 0) { 521 #ifdef CONFIG_PCI1 522 path = fdt_getprop(blob, node, "pci0", NULL); 523 if (path) { 524 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; 525 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 526 } 527 #endif 528 #ifdef CONFIG_PCIE2 529 path = fdt_getprop(blob, node, "pci1", NULL); 530 if (path) { 531 tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno; 532 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 533 } 534 #endif 535 #ifdef CONFIG_PCIE1 536 path = fdt_getprop(blob, node, "pci2", NULL); 537 if (path) { 538 tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; 539 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 540 } 541 #endif 542 #ifdef CONFIG_PCIE3 543 path = fdt_getprop(blob, node, "pci3", NULL); 544 if (path) { 545 tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno; 546 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 547 } 548 #endif 549 } 550 } 551 #endif 552