1 /* 2 * Copyright 2007 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/immap_85xx.h> 28 #include <asm/immap_fsl_pci.h> 29 #include <asm/io.h> 30 #include <spd_sdram.h> 31 #include <miiphy.h> 32 #include <libfdt.h> 33 #include <fdt_support.h> 34 35 #include "../common/pixis.h" 36 37 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 38 extern void ddr_enable_ecc(unsigned int dram_size); 39 #endif 40 41 void sdram_init(void); 42 43 int board_early_init_f (void) 44 { 45 return 0; 46 } 47 48 int checkboard (void) 49 { 50 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 51 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); 52 volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); 53 54 if ((uint)&gur->porpllsr != 0xe00e0000) { 55 printf("immap size error %x\n",&gur->porpllsr); 56 } 57 printf ("Board: MPC8544DS\n"); 58 59 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ 60 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ 61 ecm->eedr = 0xffffffff; /* Clear ecm errors */ 62 ecm->eeer = 0xffffffff; /* Enable ecm errors */ 63 64 return 0; 65 } 66 67 long int 68 initdram(int board_type) 69 { 70 long dram_size = 0; 71 72 puts("Initializing\n"); 73 74 dram_size = spd_sdram(); 75 76 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 77 /* 78 * Initialize and enable DDR ECC. 79 */ 80 ddr_enable_ecc(dram_size); 81 #endif 82 puts(" DDR: "); 83 return dram_size; 84 } 85 86 #ifdef CONFIG_PCI1 87 static struct pci_controller pci1_hose; 88 #endif 89 90 #ifdef CONFIG_PCIE1 91 static struct pci_controller pcie1_hose; 92 #endif 93 94 #ifdef CONFIG_PCIE2 95 static struct pci_controller pcie2_hose; 96 #endif 97 98 #ifdef CONFIG_PCIE3 99 static struct pci_controller pcie3_hose; 100 #endif 101 102 int first_free_busno=0; 103 104 void 105 pci_init_board(void) 106 { 107 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 108 uint devdisr = gur->devdisr; 109 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 110 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; 111 112 debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", 113 devdisr, io_sel, host_agent); 114 115 if (io_sel & 1) { 116 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) 117 printf (" eTSEC1 is in sgmii mode.\n"); 118 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) 119 printf (" eTSEC3 is in sgmii mode.\n"); 120 } 121 122 #ifdef CONFIG_PCIE3 123 { 124 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR; 125 extern void fsl_pci_init(struct pci_controller *hose); 126 struct pci_controller *hose = &pcie3_hose; 127 int pcie_ep = (host_agent == 1); 128 int pcie_configured = io_sel >= 1; 129 130 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 131 printf ("\n PCIE3 connected to ULI as %s (base address %x)", 132 pcie_ep ? "End Point" : "Root Complex", 133 (uint)pci); 134 if (pci->pme_msg_det) { 135 pci->pme_msg_det = 0xffffffff; 136 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 137 } 138 printf ("\n"); 139 140 /* inbound */ 141 pci_set_region(hose->regions + 0, 142 CFG_PCI_MEMORY_BUS, 143 CFG_PCI_MEMORY_PHYS, 144 CFG_PCI_MEMORY_SIZE, 145 PCI_REGION_MEM | PCI_REGION_MEMORY); 146 147 /* outbound memory */ 148 pci_set_region(hose->regions + 1, 149 CFG_PCIE3_MEM_BASE, 150 CFG_PCIE3_MEM_PHYS, 151 CFG_PCIE3_MEM_SIZE, 152 PCI_REGION_MEM); 153 154 /* outbound io */ 155 pci_set_region(hose->regions + 2, 156 CFG_PCIE3_IO_BASE, 157 CFG_PCIE3_IO_PHYS, 158 CFG_PCIE3_IO_SIZE, 159 PCI_REGION_IO); 160 161 hose->region_count = 3; 162 #ifdef CFG_PCIE3_MEM_BASE2 163 /* outbound memory */ 164 pci_set_region(hose->regions + 3, 165 CFG_PCIE3_MEM_BASE2, 166 CFG_PCIE3_MEM_PHYS2, 167 CFG_PCIE3_MEM_SIZE2, 168 PCI_REGION_MEM); 169 hose->region_count++; 170 #endif 171 hose->first_busno=first_free_busno; 172 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 173 174 fsl_pci_init(hose); 175 176 first_free_busno=hose->last_busno+1; 177 printf (" PCIE3 on bus %02x - %02x\n", 178 hose->first_busno,hose->last_busno); 179 180 /* 181 * Activate ULI1575 legacy chip by performing a fake 182 * memory access. Needed to make ULI RTC work. 183 */ 184 in_be32((u32 *)CFG_PCIE3_MEM_BASE); 185 } else { 186 printf (" PCIE3: disabled\n"); 187 } 188 189 } 190 #else 191 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ 192 #endif 193 194 #ifdef CONFIG_PCIE1 195 { 196 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; 197 extern void fsl_pci_init(struct pci_controller *hose); 198 struct pci_controller *hose = &pcie1_hose; 199 int pcie_ep = (host_agent == 5); 200 int pcie_configured = io_sel & 6; 201 202 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 203 printf ("\n PCIE1 connected to Slot2 as %s (base address %x)", 204 pcie_ep ? "End Point" : "Root Complex", 205 (uint)pci); 206 if (pci->pme_msg_det) { 207 pci->pme_msg_det = 0xffffffff; 208 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 209 } 210 printf ("\n"); 211 212 /* inbound */ 213 pci_set_region(hose->regions + 0, 214 CFG_PCI_MEMORY_BUS, 215 CFG_PCI_MEMORY_PHYS, 216 CFG_PCI_MEMORY_SIZE, 217 PCI_REGION_MEM | PCI_REGION_MEMORY); 218 219 /* outbound memory */ 220 pci_set_region(hose->regions + 1, 221 CFG_PCIE1_MEM_BASE, 222 CFG_PCIE1_MEM_PHYS, 223 CFG_PCIE1_MEM_SIZE, 224 PCI_REGION_MEM); 225 226 /* outbound io */ 227 pci_set_region(hose->regions + 2, 228 CFG_PCIE1_IO_BASE, 229 CFG_PCIE1_IO_PHYS, 230 CFG_PCIE1_IO_SIZE, 231 PCI_REGION_IO); 232 233 hose->region_count = 3; 234 #ifdef CFG_PCIE1_MEM_BASE2 235 /* outbound memory */ 236 pci_set_region(hose->regions + 3, 237 CFG_PCIE1_MEM_BASE2, 238 CFG_PCIE1_MEM_PHYS2, 239 CFG_PCIE1_MEM_SIZE2, 240 PCI_REGION_MEM); 241 hose->region_count++; 242 #endif 243 hose->first_busno=first_free_busno; 244 245 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 246 247 fsl_pci_init(hose); 248 249 first_free_busno=hose->last_busno+1; 250 printf(" PCIE1 on bus %02x - %02x\n", 251 hose->first_busno,hose->last_busno); 252 253 } else { 254 printf (" PCIE1: disabled\n"); 255 } 256 257 } 258 #else 259 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 260 #endif 261 262 #ifdef CONFIG_PCIE2 263 { 264 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR; 265 extern void fsl_pci_init(struct pci_controller *hose); 266 struct pci_controller *hose = &pcie2_hose; 267 int pcie_ep = (host_agent == 3); 268 int pcie_configured = io_sel & 4; 269 270 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 271 printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)", 272 pcie_ep ? "End Point" : "Root Complex", 273 (uint)pci); 274 if (pci->pme_msg_det) { 275 pci->pme_msg_det = 0xffffffff; 276 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 277 } 278 printf ("\n"); 279 280 /* inbound */ 281 pci_set_region(hose->regions + 0, 282 CFG_PCI_MEMORY_BUS, 283 CFG_PCI_MEMORY_PHYS, 284 CFG_PCI_MEMORY_SIZE, 285 PCI_REGION_MEM | PCI_REGION_MEMORY); 286 287 /* outbound memory */ 288 pci_set_region(hose->regions + 1, 289 CFG_PCIE2_MEM_BASE, 290 CFG_PCIE2_MEM_PHYS, 291 CFG_PCIE2_MEM_SIZE, 292 PCI_REGION_MEM); 293 294 /* outbound io */ 295 pci_set_region(hose->regions + 2, 296 CFG_PCIE2_IO_BASE, 297 CFG_PCIE2_IO_PHYS, 298 CFG_PCIE2_IO_SIZE, 299 PCI_REGION_IO); 300 301 hose->region_count = 3; 302 #ifdef CFG_PCIE2_MEM_BASE2 303 /* outbound memory */ 304 pci_set_region(hose->regions + 3, 305 CFG_PCIE2_MEM_BASE2, 306 CFG_PCIE2_MEM_PHYS2, 307 CFG_PCIE2_MEM_SIZE2, 308 PCI_REGION_MEM); 309 hose->region_count++; 310 #endif 311 hose->first_busno=first_free_busno; 312 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 313 314 fsl_pci_init(hose); 315 first_free_busno=hose->last_busno+1; 316 printf (" PCIE2 on bus %02x - %02x\n", 317 hose->first_busno,hose->last_busno); 318 319 } else { 320 printf (" PCIE2: disabled\n"); 321 } 322 323 } 324 #else 325 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ 326 #endif 327 328 329 #ifdef CONFIG_PCI1 330 { 331 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; 332 extern void fsl_pci_init(struct pci_controller *hose); 333 struct pci_controller *hose = &pci1_hose; 334 335 uint pci_agent = (host_agent == 6); 336 uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ 337 uint pci_32 = 1; 338 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ 339 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ 340 341 342 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 343 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n", 344 (pci_32) ? 32 : 64, 345 (pci_speed == 33333000) ? "33" : 346 (pci_speed == 66666000) ? "66" : "unknown", 347 pci_clk_sel ? "sync" : "async", 348 pci_agent ? "agent" : "host", 349 pci_arb ? "arbiter" : "external-arbiter", 350 (uint)pci 351 ); 352 353 /* inbound */ 354 pci_set_region(hose->regions + 0, 355 CFG_PCI_MEMORY_BUS, 356 CFG_PCI_MEMORY_PHYS, 357 CFG_PCI_MEMORY_SIZE, 358 PCI_REGION_MEM | PCI_REGION_MEMORY); 359 360 /* outbound memory */ 361 pci_set_region(hose->regions + 1, 362 CFG_PCI1_MEM_BASE, 363 CFG_PCI1_MEM_PHYS, 364 CFG_PCI1_MEM_SIZE, 365 PCI_REGION_MEM); 366 367 /* outbound io */ 368 pci_set_region(hose->regions + 2, 369 CFG_PCI1_IO_BASE, 370 CFG_PCI1_IO_PHYS, 371 CFG_PCI1_IO_SIZE, 372 PCI_REGION_IO); 373 hose->region_count = 3; 374 #ifdef CFG_PCIE3_MEM_BASE2 375 /* outbound memory */ 376 pci_set_region(hose->regions + 3, 377 CFG_PCIE3_MEM_BASE2, 378 CFG_PCIE3_MEM_PHYS2, 379 CFG_PCIE3_MEM_SIZE2, 380 PCI_REGION_MEM); 381 hose->region_count++; 382 #endif 383 hose->first_busno=first_free_busno; 384 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 385 386 fsl_pci_init(hose); 387 first_free_busno=hose->last_busno+1; 388 printf ("PCI on bus %02x - %02x\n", 389 hose->first_busno,hose->last_busno); 390 } else { 391 printf (" PCI: disabled\n"); 392 } 393 } 394 #else 395 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ 396 #endif 397 } 398 399 400 int last_stage_init(void) 401 { 402 return 0; 403 } 404 405 406 unsigned long 407 get_board_sys_clk(ulong dummy) 408 { 409 u8 i, go_bit, rd_clks; 410 ulong val = 0; 411 412 go_bit = in8(PIXIS_BASE + PIXIS_VCTL); 413 go_bit &= 0x01; 414 415 rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0); 416 rd_clks &= 0x1C; 417 418 /* 419 * Only if both go bit and the SCLK bit in VCFGEN0 are set 420 * should we be using the AUX register. Remember, we also set the 421 * GO bit to boot from the alternate bank on the on-board flash 422 */ 423 424 if (go_bit) { 425 if (rd_clks == 0x1c) 426 i = in8(PIXIS_BASE + PIXIS_AUX); 427 else 428 i = in8(PIXIS_BASE + PIXIS_SPD); 429 } else { 430 i = in8(PIXIS_BASE + PIXIS_SPD); 431 } 432 433 i &= 0x07; 434 435 switch (i) { 436 case 0: 437 val = 33333333; 438 break; 439 case 1: 440 val = 40000000; 441 break; 442 case 2: 443 val = 50000000; 444 break; 445 case 3: 446 val = 66666666; 447 break; 448 case 4: 449 val = 83000000; 450 break; 451 case 5: 452 val = 100000000; 453 break; 454 case 6: 455 val = 133333333; 456 break; 457 case 7: 458 val = 166666666; 459 break; 460 } 461 462 return val; 463 } 464 465 #if defined(CONFIG_OF_BOARD_SETUP) 466 467 void 468 ft_board_setup(void *blob, bd_t *bd) 469 { 470 int node, tmp[2]; 471 const char *path; 472 473 ft_cpu_setup(blob, bd); 474 475 node = fdt_path_offset(blob, "/aliases"); 476 tmp[0] = 0; 477 if (node >= 0) { 478 #ifdef CONFIG_PCI1 479 path = fdt_getprop(blob, node, "pci0", NULL); 480 if (path) { 481 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; 482 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 483 } 484 #endif 485 #ifdef CONFIG_PCIE2 486 path = fdt_getprop(blob, node, "pci1", NULL); 487 if (path) { 488 tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno; 489 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 490 } 491 #endif 492 #ifdef CONFIG_PCIE1 493 path = fdt_getprop(blob, node, "pci2", NULL); 494 if (path) { 495 tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; 496 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 497 } 498 #endif 499 #ifdef CONFIG_PCIE3 500 path = fdt_getprop(blob, node, "pci3", NULL); 501 if (path) { 502 tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno; 503 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 504 } 505 #endif 506 } 507 } 508 #endif 509