1 /* 2 * Copyright 2007,2009-2010 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/mmu.h> 28 #include <asm/immap_85xx.h> 29 #include <asm/fsl_pci.h> 30 #include <asm/fsl_ddr_sdram.h> 31 #include <asm/fsl_serdes.h> 32 #include <asm/io.h> 33 #include <miiphy.h> 34 #include <libfdt.h> 35 #include <fdt_support.h> 36 #include <tsec.h> 37 #include <netdev.h> 38 39 #include "../common/sgmii_riser.h" 40 41 int checkboard (void) 42 { 43 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 44 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 45 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 46 u8 vboot; 47 u8 *pixis_base = (u8 *)PIXIS_BASE; 48 49 if ((uint)&gur->porpllsr != 0xe00e0000) { 50 printf("immap size error %lx\n",(ulong)&gur->porpllsr); 51 } 52 printf ("Board: MPC8544DS, Sys ID: 0x%02x, " 53 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 54 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 55 in_8(pixis_base + PIXIS_PVER)); 56 57 vboot = in_8(pixis_base + PIXIS_VBOOT); 58 if (vboot & PIXIS_VBOOT_FMAP) 59 printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6)); 60 else 61 puts ("Promjet\n"); 62 63 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ 64 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ 65 ecm->eedr = 0xffffffff; /* Clear ecm errors */ 66 ecm->eeer = 0xffffffff; /* Enable ecm errors */ 67 68 return 0; 69 } 70 71 phys_size_t 72 initdram(int board_type) 73 { 74 long dram_size = 0; 75 76 puts("Initializing\n"); 77 78 dram_size = fsl_ddr_sdram(); 79 80 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 81 82 dram_size *= 0x100000; 83 84 puts(" DDR: "); 85 return dram_size; 86 } 87 88 #ifdef CONFIG_PCI1 89 static struct pci_controller pci1_hose; 90 #endif 91 92 #ifdef CONFIG_PCIE1 93 static struct pci_controller pcie1_hose; 94 #endif 95 96 #ifdef CONFIG_PCIE2 97 static struct pci_controller pcie2_hose; 98 #endif 99 100 #ifdef CONFIG_PCIE3 101 static struct pci_controller pcie3_hose; 102 #endif 103 104 void pci_init_board(void) 105 { 106 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 107 struct fsl_pci_info pci_info[4]; 108 u32 devdisr, pordevsr, io_sel; 109 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; 110 int first_free_busno = 0; 111 int num = 0; 112 113 int pcie_ep, pcie_configured; 114 115 devdisr = in_be32(&gur->devdisr); 116 pordevsr = in_be32(&gur->pordevsr); 117 porpllsr = in_be32(&gur->porpllsr); 118 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 119 120 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); 121 122 puts("\n"); 123 124 #ifdef CONFIG_PCIE3 125 pcie_configured = is_serdes_configured(PCIE3); 126 127 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ 128 SET_STD_PCIE_INFO(pci_info[num], 3); 129 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); 130 #ifdef CONFIG_SYS_PCIE3_MEM_BUS2 131 /* outbound memory */ 132 pci_set_region(&pcie3_hose.regions[0], 133 CONFIG_SYS_PCIE3_MEM_BUS2, 134 CONFIG_SYS_PCIE3_MEM_PHYS2, 135 CONFIG_SYS_PCIE3_MEM_SIZE2, 136 PCI_REGION_MEM); 137 138 pcie3_hose.region_count = 1; 139 #endif 140 printf("PCIE3: connected to ULI as %s (base addr %lx)\n", 141 pcie_ep ? "Endpoint" : "Root Complex", 142 pci_info[num].regs); 143 first_free_busno = fsl_pci_init_port(&pci_info[num++], 144 &pcie3_hose, first_free_busno); 145 146 /* 147 * Activate ULI1575 legacy chip by performing a fake 148 * memory access. Needed to make ULI RTC work. 149 */ 150 in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS); 151 } else { 152 printf("PCIE3: disabled\n"); 153 } 154 puts("\n"); 155 #else 156 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ 157 #endif 158 159 #ifdef CONFIG_PCIE1 160 pcie_configured = is_serdes_configured(PCIE1); 161 162 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 163 SET_STD_PCIE_INFO(pci_info[num], 1); 164 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); 165 #ifdef CONFIG_SYS_PCIE1_MEM_BUS2 166 /* outbound memory */ 167 pci_set_region(&pcie1_hose.regions[0], 168 CONFIG_SYS_PCIE1_MEM_BUS2, 169 CONFIG_SYS_PCIE1_MEM_PHYS2, 170 CONFIG_SYS_PCIE1_MEM_SIZE2, 171 PCI_REGION_MEM); 172 173 pcie1_hose.region_count = 1; 174 #endif 175 printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n", 176 pcie_ep ? "Endpoint" : "Root Complex", 177 pci_info[num].regs); 178 179 first_free_busno = fsl_pci_init_port(&pci_info[num++], 180 &pcie1_hose, first_free_busno); 181 } else { 182 printf("PCIE1: disabled\n"); 183 } 184 185 puts("\n"); 186 #else 187 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ 188 #endif 189 190 #ifdef CONFIG_PCIE2 191 pcie_configured = is_serdes_configured(PCIE2); 192 193 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ 194 SET_STD_PCIE_INFO(pci_info[num], 2); 195 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); 196 #ifdef CONFIG_SYS_PCIE2_MEM_BUS2 197 /* outbound memory */ 198 pci_set_region(&pcie2_hose.regions[0], 199 CONFIG_SYS_PCIE2_MEM_BUS2, 200 CONFIG_SYS_PCIE2_MEM_PHYS2, 201 CONFIG_SYS_PCIE2_MEM_SIZE2, 202 PCI_REGION_MEM); 203 204 pcie2_hose.region_count = 1; 205 #endif 206 printf("PCIE2: connected to Slot 1 as %s (base addr %lx)\n", 207 pcie_ep ? "Endpoint" : "Root Complex", 208 pci_info[num].regs); 209 first_free_busno = fsl_pci_init_port(&pci_info[num++], 210 &pcie2_hose, first_free_busno); 211 } else { 212 printf("PCIE2: disabled\n"); 213 } 214 215 puts("\n"); 216 #else 217 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ 218 #endif 219 220 #ifdef CONFIG_PCI1 221 pci_speed = 66666000; 222 pci_32 = 1; 223 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; 224 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; 225 226 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 227 SET_STD_PCI_INFO(pci_info[num], 1); 228 pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); 229 printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", 230 (pci_32) ? 32 : 64, 231 (pci_speed == 33333000) ? "33" : 232 (pci_speed == 66666000) ? "66" : "unknown", 233 pci_clk_sel ? "sync" : "async", 234 pci_agent ? "agent" : "host", 235 pci_arb ? "arbiter" : "external-arbiter", 236 pci_info[num].regs); 237 238 first_free_busno = fsl_pci_init_port(&pci_info[num++], 239 &pci1_hose, first_free_busno); 240 } else { 241 printf("PCI: disabled\n"); 242 } 243 244 puts("\n"); 245 #else 246 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ 247 #endif 248 } 249 250 251 int last_stage_init(void) 252 { 253 return 0; 254 } 255 256 257 unsigned long 258 get_board_sys_clk(ulong dummy) 259 { 260 u8 i, go_bit, rd_clks; 261 ulong val = 0; 262 u8 *pixis_base = (u8 *)PIXIS_BASE; 263 264 go_bit = in_8(pixis_base + PIXIS_VCTL); 265 go_bit &= 0x01; 266 267 rd_clks = in_8(pixis_base + PIXIS_VCFGEN0); 268 rd_clks &= 0x1C; 269 270 /* 271 * Only if both go bit and the SCLK bit in VCFGEN0 are set 272 * should we be using the AUX register. Remember, we also set the 273 * GO bit to boot from the alternate bank on the on-board flash 274 */ 275 276 if (go_bit) { 277 if (rd_clks == 0x1c) 278 i = in_8(pixis_base + PIXIS_AUX); 279 else 280 i = in_8(pixis_base + PIXIS_SPD); 281 } else { 282 i = in_8(pixis_base + PIXIS_SPD); 283 } 284 285 i &= 0x07; 286 287 switch (i) { 288 case 0: 289 val = 33333333; 290 break; 291 case 1: 292 val = 40000000; 293 break; 294 case 2: 295 val = 50000000; 296 break; 297 case 3: 298 val = 66666666; 299 break; 300 case 4: 301 val = 83000000; 302 break; 303 case 5: 304 val = 100000000; 305 break; 306 case 6: 307 val = 133333333; 308 break; 309 case 7: 310 val = 166666666; 311 break; 312 } 313 314 return val; 315 } 316 317 int board_eth_init(bd_t *bis) 318 { 319 #ifdef CONFIG_TSEC_ENET 320 struct tsec_info_struct tsec_info[2]; 321 int num = 0; 322 323 #ifdef CONFIG_TSEC1 324 SET_STD_TSEC_INFO(tsec_info[num], 1); 325 if (is_serdes_configured(SGMII_TSEC1)) { 326 puts("eTSEC1 is in sgmii mode.\n"); 327 tsec_info[num].flags |= TSEC_SGMII; 328 } 329 num++; 330 #endif 331 #ifdef CONFIG_TSEC3 332 SET_STD_TSEC_INFO(tsec_info[num], 3); 333 if (is_serdes_configured(SGMII_TSEC3)) { 334 puts("eTSEC3 is in sgmii mode.\n"); 335 tsec_info[num].flags |= TSEC_SGMII; 336 } 337 num++; 338 #endif 339 340 if (!num) { 341 printf("No TSECs initialized\n"); 342 343 return 0; 344 } 345 346 if (is_serdes_configured(SGMII_TSEC1) || 347 is_serdes_configured(SGMII_TSEC3)) { 348 fsl_sgmii_riser_init(tsec_info, num); 349 } 350 351 352 tsec_eth_init(bis, tsec_info, num); 353 #endif 354 return pci_eth_init(bis); 355 } 356 357 #if defined(CONFIG_OF_BOARD_SETUP) 358 void ft_board_setup(void *blob, bd_t *bd) 359 { 360 ft_cpu_setup(blob, bd); 361 362 FT_FSL_PCI_SETUP; 363 364 #ifdef CONFIG_FSL_SGMII_RISER 365 fsl_sgmii_riser_fdt_fixup(blob); 366 #endif 367 } 368 #endif 369