1 /* 2 * Copyright 2008 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/mmu.h> 28 #include <asm/cache.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/io.h> 33 #include <spd.h> 34 #include <miiphy.h> 35 #include <libfdt.h> 36 #include <spd_sdram.h> 37 #include <fdt_support.h> 38 #include <tsec.h> 39 #include <netdev.h> 40 #include <sata.h> 41 42 #include "../common/pixis.h" 43 #include "../common/sgmii_riser.h" 44 45 phys_size_t fixed_sdram(void); 46 47 int board_early_init_f (void) 48 { 49 #ifdef CONFIG_MMC 50 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 51 52 setbits_be32(&gur->pmuxcr, 53 (MPC85xx_PMUXCR_SD_DATA | 54 MPC85xx_PMUXCR_SDHC_CD | 55 MPC85xx_PMUXCR_SDHC_WP)); 56 57 #endif 58 return 0; 59 } 60 61 int checkboard (void) 62 { 63 u8 vboot; 64 u8 *pixis_base = (u8 *)PIXIS_BASE; 65 66 puts("Board: MPC8536DS "); 67 #ifdef CONFIG_PHYS_64BIT 68 puts("(36-bit addrmap) "); 69 #endif 70 71 printf ("Sys ID: 0x%02x, " 72 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 73 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 74 in_8(pixis_base + PIXIS_PVER)); 75 76 vboot = in_8(pixis_base + PIXIS_VBOOT); 77 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) { 78 case PIXIS_VBOOT_LBMAP_NOR0: 79 puts ("vBank: 0\n"); 80 break; 81 case PIXIS_VBOOT_LBMAP_NOR1: 82 puts ("vBank: 1\n"); 83 break; 84 case PIXIS_VBOOT_LBMAP_NOR2: 85 puts ("vBank: 2\n"); 86 break; 87 case PIXIS_VBOOT_LBMAP_NOR3: 88 puts ("vBank: 3\n"); 89 break; 90 case PIXIS_VBOOT_LBMAP_PJET: 91 puts ("Promjet\n"); 92 break; 93 case PIXIS_VBOOT_LBMAP_NAND: 94 puts ("NAND\n"); 95 break; 96 } 97 98 return 0; 99 } 100 101 phys_size_t 102 initdram(int board_type) 103 { 104 phys_size_t dram_size = 0; 105 106 puts("Initializing...."); 107 108 #ifdef CONFIG_SPD_EEPROM 109 dram_size = fsl_ddr_sdram(); 110 #else 111 dram_size = fixed_sdram(); 112 #endif 113 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 114 dram_size *= 0x100000; 115 116 puts(" DDR: "); 117 return dram_size; 118 } 119 120 #if !defined(CONFIG_SPD_EEPROM) 121 /* 122 * Fixed sdram init -- doesn't use serial presence detect. 123 */ 124 125 phys_size_t fixed_sdram (void) 126 { 127 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 128 volatile ccsr_ddr_t *ddr= &immap->im_ddr; 129 uint d_init; 130 131 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 132 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 133 134 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 135 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 136 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 137 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 138 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 139 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 140 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 141 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 142 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 143 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 144 145 #if defined (CONFIG_DDR_ECC) 146 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; 147 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; 148 ddr->err_sbe = CONFIG_SYS_DDR_SBE; 149 #endif 150 asm("sync;isync"); 151 152 udelay(500); 153 154 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 155 156 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 157 d_init = 1; 158 debug("DDR - 1st controller: memory initializing\n"); 159 /* 160 * Poll until memory is initialized. 161 * 512 Meg at 400 might hit this 200 times or so. 162 */ 163 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 164 udelay(1000); 165 } 166 debug("DDR: memory initialized\n\n"); 167 asm("sync; isync"); 168 udelay(500); 169 #endif 170 171 return 512 * 1024 * 1024; 172 } 173 174 #endif 175 176 #ifdef CONFIG_PCI1 177 static struct pci_controller pci1_hose; 178 #endif 179 180 #ifdef CONFIG_PCIE1 181 static struct pci_controller pcie1_hose; 182 #endif 183 184 #ifdef CONFIG_PCIE2 185 static struct pci_controller pcie2_hose; 186 #endif 187 188 #ifdef CONFIG_PCIE3 189 static struct pci_controller pcie3_hose; 190 #endif 191 192 int first_free_busno=0; 193 194 void 195 pci_init_board(void) 196 { 197 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 198 uint devdisr = gur->devdisr; 199 uint sdrs2_io_sel = 200 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 201 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 202 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; 203 204 debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x,\ 205 host_agent=%x\n", devdisr, sdrs2_io_sel, io_sel, host_agent); 206 207 if (sdrs2_io_sel == 7) 208 printf(" Serdes2 disalbed\n"); 209 else if (sdrs2_io_sel == 4) { 210 printf(" eTSEC1 is in sgmii mode.\n"); 211 printf(" eTSEC3 is in sgmii mode.\n"); 212 } else if (sdrs2_io_sel == 6) 213 printf(" eTSEC1 is in sgmii mode.\n"); 214 215 #ifdef CONFIG_PCIE3 216 { 217 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; 218 struct pci_controller *hose = &pcie3_hose; 219 int pcie_ep = (host_agent == 1); 220 int pcie_configured = (io_sel == 7); 221 struct pci_region *r = hose->regions; 222 223 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 224 printf ("\n PCIE3 connected to Slot3 as %s (base address %x)", 225 pcie_ep ? "End Point" : "Root Complex", 226 (uint)pci); 227 if (pci->pme_msg_det) { 228 pci->pme_msg_det = 0xffffffff; 229 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 230 } 231 printf ("\n"); 232 233 /* inbound */ 234 r += fsl_pci_setup_inbound_windows(r); 235 236 /* outbound memory */ 237 pci_set_region(r++, 238 CONFIG_SYS_PCIE3_MEM_BUS, 239 CONFIG_SYS_PCIE3_MEM_PHYS, 240 CONFIG_SYS_PCIE3_MEM_SIZE, 241 PCI_REGION_MEM); 242 243 /* outbound io */ 244 pci_set_region(r++, 245 CONFIG_SYS_PCIE3_IO_BUS, 246 CONFIG_SYS_PCIE3_IO_PHYS, 247 CONFIG_SYS_PCIE3_IO_SIZE, 248 PCI_REGION_IO); 249 250 hose->region_count = r - hose->regions; 251 252 hose->first_busno=first_free_busno; 253 254 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 255 256 first_free_busno=hose->last_busno+1; 257 printf (" PCIE3 on bus %02x - %02x\n", 258 hose->first_busno,hose->last_busno); 259 } else { 260 printf (" PCIE3: disabled\n"); 261 } 262 263 } 264 #else 265 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ 266 #endif 267 268 #ifdef CONFIG_PCIE1 269 { 270 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; 271 struct pci_controller *hose = &pcie1_hose; 272 int pcie_ep = (host_agent == 5); 273 int pcie_configured = (io_sel == 2 || io_sel == 3 274 || io_sel == 5 || io_sel == 7); 275 struct pci_region *r = hose->regions; 276 277 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 278 printf ("\n PCIE1 connected to Slot1 as %s (base address %x)", 279 pcie_ep ? "End Point" : "Root Complex", 280 (uint)pci); 281 if (pci->pme_msg_det) { 282 pci->pme_msg_det = 0xffffffff; 283 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 284 } 285 printf ("\n"); 286 287 /* inbound */ 288 r += fsl_pci_setup_inbound_windows(r); 289 290 /* outbound memory */ 291 pci_set_region(r++, 292 CONFIG_SYS_PCIE1_MEM_BUS, 293 CONFIG_SYS_PCIE1_MEM_PHYS, 294 CONFIG_SYS_PCIE1_MEM_SIZE, 295 PCI_REGION_MEM); 296 297 /* outbound io */ 298 pci_set_region(r++, 299 CONFIG_SYS_PCIE1_IO_BUS, 300 CONFIG_SYS_PCIE1_IO_PHYS, 301 CONFIG_SYS_PCIE1_IO_SIZE, 302 PCI_REGION_IO); 303 304 #ifdef CONFIG_SYS_PCIE1_MEM_BUS2 305 /* outbound memory */ 306 pci_set_region(r++, 307 CONFIG_SYS_PCIE1_MEM_BUS2, 308 CONFIG_SYS_PCIE1_MEM_PHYS2, 309 CONFIG_SYS_PCIE1_MEM_SIZE2, 310 PCI_REGION_MEM); 311 #endif 312 hose->region_count = r - hose->regions; 313 hose->first_busno=first_free_busno; 314 315 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 316 317 first_free_busno=hose->last_busno+1; 318 printf(" PCIE1 on bus %02x - %02x\n", 319 hose->first_busno,hose->last_busno); 320 321 } else { 322 printf (" PCIE1: disabled\n"); 323 } 324 325 } 326 #else 327 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 328 #endif 329 330 #ifdef CONFIG_PCIE2 331 { 332 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; 333 struct pci_controller *hose = &pcie2_hose; 334 int pcie_ep = (host_agent == 3); 335 int pcie_configured = (io_sel == 5 || io_sel == 7); 336 struct pci_region *r = hose->regions; 337 338 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 339 printf ("\n PCIE2 connected to Slot 2 as %s (base address %x)", 340 pcie_ep ? "End Point" : "Root Complex", 341 (uint)pci); 342 if (pci->pme_msg_det) { 343 pci->pme_msg_det = 0xffffffff; 344 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 345 } 346 printf ("\n"); 347 348 /* inbound */ 349 r += fsl_pci_setup_inbound_windows(r); 350 351 /* outbound memory */ 352 pci_set_region(r++, 353 CONFIG_SYS_PCIE2_MEM_BUS, 354 CONFIG_SYS_PCIE2_MEM_PHYS, 355 CONFIG_SYS_PCIE2_MEM_SIZE, 356 PCI_REGION_MEM); 357 358 /* outbound io */ 359 pci_set_region(r++, 360 CONFIG_SYS_PCIE2_IO_BUS, 361 CONFIG_SYS_PCIE2_IO_PHYS, 362 CONFIG_SYS_PCIE2_IO_SIZE, 363 PCI_REGION_IO); 364 365 #ifdef CONFIG_SYS_PCIE2_MEM_BUS2 366 /* outbound memory */ 367 pci_set_region(r++, 368 CONFIG_SYS_PCIE2_MEM_BUS2, 369 CONFIG_SYS_PCIE2_MEM_PHYS2, 370 CONFIG_SYS_PCIE2_MEM_SIZE2, 371 PCI_REGION_MEM); 372 #endif 373 hose->region_count = r - hose->regions; 374 hose->first_busno=first_free_busno; 375 376 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 377 first_free_busno=hose->last_busno+1; 378 printf (" PCIE2 on bus %02x - %02x\n", 379 hose->first_busno,hose->last_busno); 380 381 } else { 382 printf (" PCIE2: disabled\n"); 383 } 384 385 } 386 #else 387 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ 388 #endif 389 390 391 #ifdef CONFIG_PCI1 392 { 393 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; 394 struct pci_controller *hose = &pci1_hose; 395 struct pci_region *r = hose->regions; 396 397 uint pci_agent = (host_agent == 6); 398 uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ 399 uint pci_32 = 1; 400 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ 401 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ 402 403 404 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 405 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n", 406 (pci_32) ? 32 : 64, 407 (pci_speed == 33333000) ? "33" : 408 (pci_speed == 66666000) ? "66" : "unknown", 409 pci_clk_sel ? "sync" : "async", 410 pci_agent ? "agent" : "host", 411 pci_arb ? "arbiter" : "external-arbiter", 412 (uint)pci 413 ); 414 415 /* inbound */ 416 r += fsl_pci_setup_inbound_windows(r); 417 418 /* outbound memory */ 419 pci_set_region(r++, 420 CONFIG_SYS_PCI1_MEM_BUS, 421 CONFIG_SYS_PCI1_MEM_PHYS, 422 CONFIG_SYS_PCI1_MEM_SIZE, 423 PCI_REGION_MEM); 424 425 /* outbound io */ 426 pci_set_region(r++, 427 CONFIG_SYS_PCI1_IO_BUS, 428 CONFIG_SYS_PCI1_IO_PHYS, 429 CONFIG_SYS_PCI1_IO_SIZE, 430 PCI_REGION_IO); 431 432 #ifdef CONFIG_SYS_PCI1_MEM_BUS2 433 /* outbound memory */ 434 pci_set_region(r++, 435 CONFIG_SYS_PCI1_MEM_BUS2, 436 CONFIG_SYS_PCI1_MEM_PHYS2, 437 CONFIG_SYS_PCI1_MEM_SIZE2, 438 PCI_REGION_MEM); 439 #endif 440 hose->region_count = r - hose->regions; 441 hose->first_busno=first_free_busno; 442 443 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 444 first_free_busno=hose->last_busno+1; 445 printf ("PCI on bus %02x - %02x\n", 446 hose->first_busno,hose->last_busno); 447 } else { 448 printf (" PCI: disabled\n"); 449 } 450 } 451 #else 452 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ 453 #endif 454 } 455 456 457 int board_early_init_r(void) 458 { 459 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 460 const u8 flash_esel = 1; 461 462 /* 463 * Remap Boot flash + PROMJET region to caching-inhibited 464 * so that flash can be erased properly. 465 */ 466 467 /* Flush d-cache and invalidate i-cache of any FLASH data */ 468 flush_dcache(); 469 invalidate_icache(); 470 471 /* invalidate existing TLB entry for flash + promjet */ 472 disable_tlb(flash_esel); 473 474 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 475 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 476 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 477 478 return 0; 479 } 480 481 #ifdef CONFIG_GET_CLK_FROM_ICS307 482 /* decode S[0-2] to Output Divider (OD) */ 483 static unsigned char 484 ics307_S_to_OD[] = { 485 10, 2, 8, 4, 5, 7, 3, 6 486 }; 487 488 /* Calculate frequency being generated by ICS307-02 clock chip based upon 489 * the control bytes being programmed into it. */ 490 /* XXX: This function should probably go into a common library */ 491 static unsigned long 492 ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2) 493 { 494 const unsigned long long InputFrequency = CONFIG_ICS307_REFCLK_HZ; 495 unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); 496 unsigned long RDW = cw2 & 0x7F; 497 unsigned long OD = ics307_S_to_OD[cw0 & 0x7]; 498 unsigned long freq; 499 500 /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */ 501 502 /* cw0: C1 C0 TTL F1 F0 S2 S1 S0 503 * cw1: V8 V7 V6 V5 V4 V3 V2 V1 504 * cw2: V0 R6 R5 R4 R3 R2 R1 R0 505 * 506 * R6:R0 = Reference Divider Word (RDW) 507 * V8:V0 = VCO Divider Word (VDW) 508 * S2:S0 = Output Divider Select (OD) 509 * F1:F0 = Function of CLK2 Output 510 * TTL = duty cycle 511 * C1:C0 = internal load capacitance for cyrstal 512 */ 513 514 /* Adding 1 to get a "nicely" rounded number, but this needs 515 * more tweaking to get a "properly" rounded number. */ 516 517 freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)); 518 519 debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2, 520 freq); 521 return freq; 522 } 523 524 unsigned long 525 get_board_sys_clk(ulong dummy) 526 { 527 u8 *pixis_base = (u8 *)PIXIS_BASE; 528 529 return ics307_clk_freq ( 530 in_8(pixis_base + PIXIS_VSYSCLK0), 531 in_8(pixis_base + PIXIS_VSYSCLK1), 532 in_8(pixis_base + PIXIS_VSYSCLK2) 533 ); 534 } 535 536 unsigned long 537 get_board_ddr_clk(ulong dummy) 538 { 539 u8 *pixis_base = (u8 *)PIXIS_BASE; 540 541 return ics307_clk_freq ( 542 in_8(pixis_base + PIXIS_VDDRCLK0), 543 in_8(pixis_base + PIXIS_VDDRCLK1), 544 in_8(pixis_base + PIXIS_VDDRCLK2) 545 ); 546 } 547 #else 548 unsigned long 549 get_board_sys_clk(ulong dummy) 550 { 551 u8 i; 552 ulong val = 0; 553 u8 *pixis_base = (u8 *)PIXIS_BASE; 554 555 i = in_8(pixis_base + PIXIS_SPD); 556 i &= 0x07; 557 558 switch (i) { 559 case 0: 560 val = 33333333; 561 break; 562 case 1: 563 val = 40000000; 564 break; 565 case 2: 566 val = 50000000; 567 break; 568 case 3: 569 val = 66666666; 570 break; 571 case 4: 572 val = 83333333; 573 break; 574 case 5: 575 val = 100000000; 576 break; 577 case 6: 578 val = 133333333; 579 break; 580 case 7: 581 val = 166666666; 582 break; 583 } 584 585 return val; 586 } 587 588 unsigned long 589 get_board_ddr_clk(ulong dummy) 590 { 591 u8 i; 592 ulong val = 0; 593 u8 *pixis_base = (u8 *)PIXIS_BASE; 594 595 i = in_8(pixis_base + PIXIS_SPD); 596 i &= 0x38; 597 i >>= 3; 598 599 switch (i) { 600 case 0: 601 val = 33333333; 602 break; 603 case 1: 604 val = 40000000; 605 break; 606 case 2: 607 val = 50000000; 608 break; 609 case 3: 610 val = 66666666; 611 break; 612 case 4: 613 val = 83333333; 614 break; 615 case 5: 616 val = 100000000; 617 break; 618 case 6: 619 val = 133333333; 620 break; 621 case 7: 622 val = 166666666; 623 break; 624 } 625 return val; 626 } 627 #endif 628 629 int sata_initialize(void) 630 { 631 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 632 uint sdrs2_io_sel = 633 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 634 if (sdrs2_io_sel & 0x04) 635 return 1; 636 637 return __sata_initialize(); 638 } 639 640 int board_eth_init(bd_t *bis) 641 { 642 #ifdef CONFIG_TSEC_ENET 643 struct tsec_info_struct tsec_info[2]; 644 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 645 int num = 0; 646 uint sdrs2_io_sel = 647 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 648 649 #ifdef CONFIG_TSEC1 650 SET_STD_TSEC_INFO(tsec_info[num], 1); 651 if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) { 652 tsec_info[num].phyaddr = 0; 653 tsec_info[num].flags |= TSEC_SGMII; 654 } 655 num++; 656 #endif 657 #ifdef CONFIG_TSEC3 658 SET_STD_TSEC_INFO(tsec_info[num], 3); 659 if (sdrs2_io_sel == 4) { 660 tsec_info[num].phyaddr = 1; 661 tsec_info[num].flags |= TSEC_SGMII; 662 } 663 num++; 664 #endif 665 666 if (!num) { 667 printf("No TSECs initialized\n"); 668 return 0; 669 } 670 671 #ifdef CONFIG_FSL_SGMII_RISER 672 if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) 673 fsl_sgmii_riser_init(tsec_info, num); 674 #endif 675 676 tsec_eth_init(bis, tsec_info, num); 677 #endif 678 return pci_eth_init(bis); 679 } 680 681 #if defined(CONFIG_OF_BOARD_SETUP) 682 void ft_board_setup(void *blob, bd_t *bd) 683 { 684 ft_cpu_setup(blob, bd); 685 686 #ifdef CONFIG_PCI1 687 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); 688 #endif 689 #ifdef CONFIG_PCIE2 690 ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); 691 #endif 692 #ifdef CONFIG_PCIE2 693 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); 694 #endif 695 #ifdef CONFIG_PCIE1 696 ft_fsl_pci_setup(blob, "pci3", &pcie3_hose); 697 #endif 698 #ifdef CONFIG_FSL_SGMII_RISER 699 fsl_sgmii_riser_fdt_fixup(blob); 700 #endif 701 } 702 #endif 703